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Diffstat (limited to 'hardware-v2/ram-ice.rep')
| -rw-r--r-- | hardware-v2/ram-ice.rep | 230 |
1 files changed, 230 insertions, 0 deletions
diff --git a/hardware-v2/ram-ice.rep b/hardware-v2/ram-ice.rep new file mode 100644 index 0000000..187b1dd --- /dev/null +++ b/hardware-v2/ram-ice.rep @@ -0,0 +1,230 @@ +Data Exported from: /home/trygvis/dev/io.trygvis/2013/02/ram-ice/hardware/ram-ice.brd +with: /home/trygvis/opt/eagle/eagle-6.4.0/ulp/statistic-brd.ulp Version 1.3.8 +at: 2/17/13 2:23 AM +EAGLE Version 6.4.0 Copyright (c) 1988-2013 CadSoft + +all Values in mm +max. Board length (Layer 20) +X = 100.00 +Y = 80.00 +Outline contour = 360.00 + +used layers 2 + + 1 Top +16 Bottom +_________________________ + +471 Wire(s) incl. Arc(s) +0 Polygon(s) +_________________________ +102 SMD(s) top +0 SMD(s) bottom +=================== +102 SMD(s) total + +34 PAD(s) +_________________________ +45 Via +0 Hole +=================== +79 Drills total +_________________________ +102 tCream +0 bCream +_________________________ +Routing Info: +36 Signal(s) +136 PAD/SMD total +=================== +132 PAD/SMD on Signal +_________________________ +Packages used area: +~ 1144.55 mm² (0.114 dm²) +_________________________ + + +============================ + +============================ +13 Elements: 0 locked / 13 unlocked +0 Testpoints (TP) + +---------------------------- +LAYER +Nb. Name Used + 1 Top 1 + 16 Bottom 1 + 17 Pads 1 + 18 Vias 1 + 19 Unrouted 0 + 20 Dimension 1 + 21 tPlace 1 + 22 bPlace 0 + 23 tOrigins 1 + 24 bOrigins 0 + 25 tNames 1 + 26 bNames 0 + 27 tValues 1 + 28 bValues 0 + 29 tStop 1 + 30 bStop 1 + 31 tCream 1 + 32 bCream 0 + 33 tFinish 0 + 34 bFinish 0 + 35 tGlue 1 + 36 bGlue 0 + 37 tTest 0 + 38 bTest 0 + 39 tKeepout 1 + 40 bKeepout 0 + 41 tRestrict 0 + 42 bRestrict 0 + 43 vRestrict 0 + 44 Drills 1 + 45 Holes 0 + 46 Milling 0 + 47 Measures 0 + 48 Document 0 + 49 Reference 0 + 51 tDocu 1 + 52 bDocu 0 + +---------------------------- +CLASS +# Name min. Width Clearance min. Drill Used +0 default 0.0000 0.0000 0.0000 36 + +---------------------------- +WIDTH +WIRE Q. +0.4064 471 + +ARC Q. + * Wire width are saved in 0.2 micron resolution. + +POLY. width Q. + +POLY. Isol. Q. + +Polygon +Type Name Layer Rank Width + * Wire width are saved in 0.2 micron resolution. + +---------------------------- +CIRCLE (width) Q. + +CIRCLE diam. Q. + +---------------------------- +TEXT (w) Q. + +TEXT (s) Q. + +---------------------------- +SMD x SMD y Roundn. Q. +1.6000 1.8000 0% 10 +0.6604 2.0320 0% 64 +0.7620 1.5240 0% 28 + +PAD tDiam Q. +1.5240 34 + +PAD bDiam Q. +1.5240 34 + +PAD tRestring Q. +0.2540 34 + +PAD bRestring Q. +0.2540 34 + +PAD iDiam Q. +1.5240 34 + +PAD iRestring Q. +0.2540 34 + +VIA Outer-Diam Q. +1.0064 45 + +VIA Outer-Restring Q. +0.2032 45 + +VIA Inner-Diam. Q. +1.0064 45 + +VIA Inner-Restring Q. +0.2032 45 + +VIA drill Q. +0.6000 45 + +VIA Stack Q. +01-16 45 +01-16-PAD 34 + +PAD drill Q. +1.0160 34 + +---------------------------- +HOLE drill Q. + +RACK +T01 0.6 +T02 1.0 + +---------------------------- +LIBRARY Q. +resistor 5 +74xx-eu 4 +memory-idt 1 +con-lstb 1 +con-molex 2 + +PACKAGE Q. +C1206 5 +SO16 4 +SO28-3 1 +MA06-1 1 +70543-14 2 + +VALUE PAC Q. Top Bot +~/-empty-/~C1 C1206 1 1 0 +~/-empty-/~C2 C1206 1 1 0 +~/-empty-/~C3 C1206 1 1 0 +~/-empty-/~C4 C1206 1 1 0 +~/-empty-/~C5 C1206 1 1 0 +74AC165D SO16 1 1 0 +74HC595D SO16 3 3 0 +~/-empty-/~IC5 SO28-3 1 1 0 +~/-empty-/~SV1 MA06-1 1 1 0 +C-GRID-14-70543 70543-14 2 2 0 + +---------------------------- +RECT x RECT y Q. +0 RECT (copper) + +---------------------------- +RECT Layer Q. + +---------------------------- +TEXT (s) Q. +0 TEXT size (copper) + +TEXT (w) Q. +0 TEXT wire width (copper) + +TEXT Q. +1.2700 16 +1.7780 1 +1.0160 2 +0.8128 2 +4 TEXT size (place) +4 TEXT wire width (place) + +CIRCLE diam. Q. +0 CIRCLE (copper) + +End report |