1 files changed, 35 insertions, 34 deletions

diff --git a/vhdl/mcu_interface_tb.vhd b/vhdl/mcu_interface_tb.vhd
index d46df95..8fa12a9 100644
--- a/vhdl/mcu_interface_tb.vhd
+++ b/vhdl/mcu_interface_tb.vhd
@@ -1,26 +1,24 @@
 library ieee;
 use ieee.std_logic_1164.all;
-use work.all;
 
--- library std;
--- use std.textio.all;
-
--- use ieee.std_logic_textio.all;
 library ieee_proposed;
 use ieee_proposed.std_logic_1164_additions.all;
 
+use work.mcu.all;
+
 entity mcu_interface_tb is
 end mcu_interface_tb;
 
 -- The MCU has to initialize its output to these values.
 architecture behaviour of mcu_interface_tb is
-  signal bit_in         : std_logic;
+  signal mcu_in         : mcu_in;
+--  signal bit_in         : std_logic;
   signal bit_out        : std_logic;
-  signal bit_clk        : std_logic := '0';
-  signal byte_out_clk   : std_logic := '0';
-  signal byte_in_clk    : std_logic := '1'; -- active low
-  signal a_oe           : std_logic := '1';
-  signal d_oe           : std_logic := '1';
+--  signal bit_clk        : std_logic := '0';
+--  signal byte_out_clk   : std_logic := '0';
+--  signal byte_in_clk    : std_logic := '1'; -- active low
+--  signal a_oe           : std_logic := '1';
+--  signal d_oe           : std_logic := '1';
 
   signal ah             : std_logic_vector(7 downto 0);
   signal al             : std_logic_vector(7 downto 0);
@@ -29,16 +27,11 @@ architecture behaviour of mcu_interface_tb is
 
   signal byte_in_s      : std_logic_vector(7 downto 0) := "UUUUUUUU";
 
-  constant tClk         : time :=  1 ns;
+  constant tClk         : time := tClk;
 begin
   mcu_interface : entity work.mcu_interface port map(
-        bit_in,
+        mcu_in,
         bit_out,
-        bit_clk,
-        byte_out_clk,
-        byte_in_clk,
-        a_oe,
-        d_oe,
         ah,
         al,
         d_out,
@@ -51,35 +44,29 @@ begin
     procedure byte_out(byte : in std_logic_vector(7 downto 0)) is
     begin
       for i in byte'range loop
-        bit_in  <= byte(i);
-        bit_clk <= '1';
+        mcu_in.bit_in  <= byte(i);
+        mcu_in.bit_clk <= '0';
         wait for tClk;
 
-        bit_clk <= '0';
+        mcu_in.bit_clk <= '1';
         wait for tClk;
       end loop;
-
-      byte_out_clk <= '1';
-      wait for tClk;
-
-      byte_out_clk <= '0';
-      wait for tClk;
     end;
 
     procedure byte_in(byte : out std_logic_vector(7 downto 0)) is
     begin
-      byte_in_clk <= '0';
+      mcu_in.byte_in_clk <= '0';
       wait for tClk;
 
-      byte_in_clk <= '1';
+      mcu_in.byte_in_clk <= '1';
       wait for tClk;
 
       for i in byte'range loop
         byte(i) := bit_out;
-        bit_clk <= '1';
+        mcu_in.bit_clk <= '0';
         wait for tClk;
 
-        bit_clk <= '0';
+        mcu_in.bit_clk <= '1';
         wait for tClk;
       end loop;
     end;
@@ -88,18 +75,32 @@ begin
       data      : in std_logic_vector(7 downto 0);
       address   : in std_logic_vector(15 downto 0)) is
     begin
-      report "write_ram: " & to_string(data);
+      report "write_ram: " & to_string(data) & "b/0x"  & to_hex_string(data) & "@" & to_hex_string(address);
 
       -- TODO: busreq + wait for busack
       byte_out(data);
       byte_out(address(7 downto 0));
       byte_out(address(15 downto 8));
+
+      mcu_in.byte_out_clk <= '0';
+      wait for tClk;
+
+      mcu_in.byte_out_clk <= '1';
+      wait for tClk;
     end;
 
   begin
+--    mcu_in.bit_in <= '0';
+--    mcu_in.bit_clk <= '1';
+--    mcu_in.byte_out_clk <= '1';
+--    mcu_in.byte_in_clk <= '1';
+--    mcu_in.a_oe <= '1';
+--    mcu_in.d_oe <= '1';
+    mcu_in <= mcu_in_initial;
+
     write_ram("10100101", "0000000000000001");
-    d_oe <= '0';
-    a_oe <= '0';
+    mcu_in.d_oe <= '0';
+    mcu_in.a_oe <= '0';
 
     wait for tClk;
     assert ah = "00000000" report "ah failed";