From 2be1fada10bddbbabe4da448a76f1208aed53c5e Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Sun, 10 Feb 2013 22:00:43 +0100
Subject: wip

---
 hardware-v1/.gitignore   |    4 +
 hardware-v1/eagle.epf    |  352 +++++++++++++
 hardware-v1/ram-ice.brd  |  814 ++++++++++++++++++++++++++++++
 hardware-v1/ram-ice.sch  | 1228 ++++++++++++++++++++++++++++++++++++++++++++++
 hardware-v1/untitled.pro |   25 +
 5 files changed, 2423 insertions(+)
 create mode 100644 hardware-v1/.gitignore
 create mode 100644 hardware-v1/eagle.epf
 create mode 100644 hardware-v1/ram-ice.brd
 create mode 100644 hardware-v1/ram-ice.sch
 create mode 100644 hardware-v1/untitled.pro

(limited to 'hardware-v1')

diff --git a/hardware-v1/.gitignore b/hardware-v1/.gitignore
new file mode 100644
index 0000000..ba66ed2
--- /dev/null
+++ b/hardware-v1/.gitignore
@@ -0,0 +1,4 @@
+*.b#*
+*.s#*
+*.pro
+eagle.epf
diff --git a/hardware-v1/eagle.epf b/hardware-v1/eagle.epf
new file mode 100644
index 0000000..ff48142
--- /dev/null
+++ b/hardware-v1/eagle.epf
@@ -0,0 +1,352 @@
+[Eagle]
+Version="06 04 00"
+Platform="Linux"
+Serial="62191E841E-LSR-WLM-1EL"
+Globals="Globals"
+Desktop="Desktop"
+
+[Globals]
+AutoSaveProject=1
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/19inch.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/40xx.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/41xx.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/45xx.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74ac-logic.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74ttl-din.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-eu.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-little-de.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-little-us.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/74xx-us.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/751xx.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/advanced-test-technologies.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/agilent-technologies.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/allegro.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-cyclone-II.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-cyclone-III.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera-stratix-iv.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/altera.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/am29-memory.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/analog-devices.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/austriamicrosystems.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/axis.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/battery.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/belton-engineering.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/buzzer.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/memory-samsung.lbr"
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+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-infineon.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-intel.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-mc68000.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-motorola.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-philips.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-renesas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-samsung.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micro-siemens.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/microchip.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micron.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/micronas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/microphon.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/microwave.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/midori-sensor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/minicircuits.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/mitsubishi-semiconductor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/motorola-sensor-driver.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/murata-filter.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/murata-sensor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/nanotec.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/national-instruments.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/national-semiconductor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/nec-lqfp100-pack.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/nec.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/nrj-semiconductor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/omnivision.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/on-semiconductor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-honeywell-3000.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-honeywell-4000.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-honeywell.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-micro-linear.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-trans-siemens.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-transmittter-hp.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/opto-vishay.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/optocoupler.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pal.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/philips-semiconductors.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/photo-elements.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/piher.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pinhead.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/plcc-socket.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pld-intel.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/plxtech.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pot-vitrohm.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pot-xicor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/pot.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/ptc-ntc.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/quantum-research-group.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rcl.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/recom-international.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rectifier.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/ref-packages-longpad.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/ref-packages.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/relay.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/renesas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-bourns.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-dil.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-net.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-power.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-ruf.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-shunt.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor-sil.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/resistor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rf-micro-devices.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rf-solutions.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/rohm.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/semicon-smd-ipc.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sensor-comus-group.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sensor-heraeus.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sensor-infratec.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sharp.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/silabs.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sim-technology.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/sipex.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/smd-ipc.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/smd-special.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/solomon-systech.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/solpad.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/special-drill.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/special.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/st-microelectronics.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/supertex.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/supply1.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/supply2.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-alps.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-coto.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-dil.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-misc.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-omron.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-raychem.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch-reed.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/switch.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/telcom.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/telecontrolli.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/telefunken.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/testpad.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/texas-sn55-sn75.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/texas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/toshiba.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/traco-electronic.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo-bei.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo-hammondmfg.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo-siemens.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo-xicon.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trafo.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transformer-pulse.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-fet.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-neu-to92.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-npn.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-pnp.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-power.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor-small-signal.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/transistor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/triac.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/trimble.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/tripas.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/u-blox.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/uln-udn.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/v-reg-micrel.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/v-reg.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/varistor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/wafer-scale-psd.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/wirepad.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xicor.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xilinx-virtex-v5.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xilinx-xc18v.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xilinx-xc9.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/xilinx-xcv.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/zetex.lbr"
+UsedLibrary="/home/trygvis/opt/eagle/eagle-6.4.0/lbr/zilog.lbr"
+
+[Win_1]
+Type="Control Panel"
+Loc="0 0 1917 1197"
+State=2
+Number=0
+
+[Desktop]
+Screen="1920 1200"
+Window="Win_1"
diff --git a/hardware-v1/ram-ice.brd b/hardware-v1/ram-ice.brd
new file mode 100644
index 0000000..0d74c93
--- /dev/null
+++ b/hardware-v1/ram-ice.brd
@@ -0,0 +1,814 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.4">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.025" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.025" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="yes"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="yes"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="yes"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="yes"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="yes"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="yes"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="yes"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="yes"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="yes"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="yes"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="no" active="yes"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="yes"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="yes"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="yes"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="yes"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="yes"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="yes"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="yes"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="no" active="yes"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="no" active="no"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="no" active="no"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="no"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="no" active="no"/>
+<layer number="95" name="Names" color="7" fill="1" visible="no" active="no"/>
+<layer number="96" name="Values" color="7" fill="1" visible="no" active="no"/>
+<layer number="97" name="Info" color="7" fill="1" visible="no" active="no"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="no" active="no"/>
+</layers>
+<board>
+<plain>
+<wire x1="0" y1="0" x2="100" y2="0" width="0" layer="20"/>
+<wire x1="100" y1="0" x2="100" y2="80" width="0" layer="20"/>
+<wire x1="100" y1="80" x2="0" y2="80" width="0" layer="20"/>
+<wire x1="0" y1="80" x2="0" y2="0" width="0" layer="20"/>
+</plain>
+<libraries>
+<library name="74xx-eu">
+<description>&lt;b&gt;TTL Devices, 74xx Series with European Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="SO16">
+<description>&lt;b&gt;Small Outline package&lt;/b&gt; 150 mil</description>
+<wire x1="4.699" y1="1.9558" x2="-4.699" y2="1.9558" width="0.1524" layer="51"/>
+<wire x1="4.699" y1="-1.9558" x2="5.08" y2="-1.5748" width="0.1524" layer="21" curve="90"/>
+<wire x1="-5.08" y1="1.5748" x2="-4.699" y2="1.9558" width="0.1524" layer="21" curve="-90"/>
+<wire x1="4.699" y1="1.9558" x2="5.08" y2="1.5748" width="0.1524" layer="21" curve="-90"/>
+<wire x1="-5.08" y1="-1.5748" x2="-4.699" y2="-1.9558" width="0.1524" layer="21" curve="90"/>
+<wire x1="-4.699" y1="-1.9558" x2="4.699" y2="-1.9558" width="0.1524" layer="51"/>
+<wire x1="5.08" y1="-1.5748" x2="5.08" y2="1.5748" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="1.5748" x2="-5.08" y2="0.508" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.508" x2="-5.08" y2="-0.508" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="-0.508" x2="-5.08" y2="-1.5748" width="0.1524" layer="21"/>
+<wire x1="-5.08" y1="0.508" x2="-5.08" y2="-0.508" width="0.1524" layer="21" curve="-180"/>
+<wire x1="-5.08" y1="-1.6002" x2="5.08" y2="-1.6002" width="0.0508" layer="21"/>
+<smd name="1" x="-4.445" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
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+<smd name="13" x="-0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="5" x="0.635" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="12" x="0.635" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="6" x="1.905" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="7" x="3.175" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="11" x="1.905" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="10" x="3.175" y="3.0734" dx="0.6604" dy="2.032" layer="1"/>
+<smd name="8" x="4.445" y="-3.0734" dx="0.6604" dy="2.032" layer="1"/>
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+<text x="-3.81" y="-0.762" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-5.461" y="-1.905" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<rectangle x1="-0.889" y1="1.9558" x2="-0.381" y2="3.0988" layer="51"/>
+<rectangle x1="-4.699" y1="-3.0988" x2="-4.191" y2="-1.9558" layer="51"/>
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+<rectangle x1="1.651" y1="-3.0988" x2="2.159" y2="-1.9558" layer="51"/>
+<rectangle x1="2.921" y1="-3.0988" x2="3.429" y2="-1.9558" layer="51"/>
+<rectangle x1="4.191" y1="-3.0988" x2="4.699" y2="-1.9558" layer="51"/>
+<rectangle x1="0.381" y1="1.9558" x2="0.889" y2="3.0988" layer="51"/>
+<rectangle x1="1.651" y1="1.9558" x2="2.159" y2="3.0988" layer="51"/>
+<rectangle x1="2.921" y1="1.9558" x2="3.429" y2="3.0988" layer="51"/>
+<rectangle x1="4.191" y1="1.9558" x2="4.699" y2="3.0988" layer="51"/>
+</package>
+</packages>
+</library>
+<library name="memory-idt">
+<description>&lt;b&gt;IDT Memories&lt;/b&gt;&lt;p&gt;
+Integrated Device Technology, Inc.&lt;p&gt;
+http://www.idt.com&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL28-6">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt; 0.6 inch</description>
+<wire x1="-17.653" y1="-1.27" x2="-17.653" y2="-6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="1.27" x2="-17.653" y2="-1.27" width="0.1524" layer="21" curve="-180"/>
+<wire x1="17.653" y1="-6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="6.604" x2="-17.653" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="-6.604" x2="17.653" y2="-6.604" width="0.1524" layer="21"/>
+<pad name="1" x="-16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="17" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="25" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="26" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="27" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="28" x="-16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-17.78" y="-6.35" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-14.605" y="-0.9398" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="SO28-3">
+<description>&lt;b&gt;Small Outline Package&lt;/b&gt;</description>
+<wire x1="-8.814" y1="-4.248" x2="8.839" y2="-4.248" width="0.1524" layer="21"/>
+<wire x1="8.839" y1="-4.248" x2="8.839" y2="4.248" width="0.1524" layer="21"/>
+<wire x1="8.839" y1="4.248" x2="-8.814" y2="4.248" width="0.1524" layer="21"/>
+<wire x1="-8.814" y1="4.248" x2="-8.814" y2="-4.248" width="0.1524" layer="21"/>
+<circle x="-7.874" y="-3.0988" radius="0.5334" width="0.1524" layer="21"/>
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+<rectangle x1="-8.509" y1="4.2735" x2="-8.001" y2="5.7975" layer="51"/>
+</package>
+</packages>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<designrules name="default">
+<description language="en">&lt;b&gt;EAGLE Design Rules&lt;/b&gt;
+&lt;p&gt;
+The default Design Rules have been set to cover
+a wide range of applications. Your particular design
+may have different requirements, so please make the
+necessary adjustments and save your customized
+design rules under a new name.
+</description>
+<param name="layerSetup" value="(1*16)"/>
+<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/>
+<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/>
+<param name="mdWireWire" value="8mil"/>
+<param name="mdWirePad" value="8mil"/>
+<param name="mdWireVia" value="8mil"/>
+<param name="mdPadPad" value="8mil"/>
+<param name="mdPadVia" value="8mil"/>
+<param name="mdViaVia" value="8mil"/>
+<param name="mdSmdPad" value="8mil"/>
+<param name="mdSmdVia" value="8mil"/>
+<param name="mdSmdSmd" value="8mil"/>
+<param name="mdViaViaSameLayer" value="8mil"/>
+<param name="mnLayersViaInSmd" value="2"/>
+<param name="mdCopperDimension" value="40mil"/>
+<param name="mdDrill" value="8mil"/>
+<param name="mdSmdStop" value="0mil"/>
+<param name="msWidth" value="10mil"/>
+<param name="msDrill" value="0.6mm"/>
+<param name="msMicroVia" value="9.99mm"/>
+<param name="msBlindViaRatio" value="0.5"/>
+<param name="rvPadTop" value="0.25"/>
+<param name="rvPadInner" value="0.25"/>
+<param name="rvPadBottom" value="0.25"/>
+<param name="rvViaOuter" value="0.25"/>
+<param name="rvViaInner" value="0.25"/>
+<param name="rvMicroViaOuter" value="0.25"/>
+<param name="rvMicroViaInner" value="0.25"/>
+<param name="rlMinPadTop" value="10mil"/>
+<param name="rlMaxPadTop" value="20mil"/>
+<param name="rlMinPadInner" value="10mil"/>
+<param name="rlMaxPadInner" value="20mil"/>
+<param name="rlMinPadBottom" value="10mil"/>
+<param name="rlMaxPadBottom" value="20mil"/>
+<param name="rlMinViaOuter" value="8mil"/>
+<param name="rlMaxViaOuter" value="20mil"/>
+<param name="rlMinViaInner" value="8mil"/>
+<param name="rlMaxViaInner" value="20mil"/>
+<param name="rlMinMicroViaOuter" value="4mil"/>
+<param name="rlMaxMicroViaOuter" value="20mil"/>
+<param name="rlMinMicroViaInner" value="4mil"/>
+<param name="rlMaxMicroViaInner" value="20mil"/>
+<param name="psTop" value="-1"/>
+<param name="psBottom" value="-1"/>
+<param name="psFirst" value="-1"/>
+<param name="psElongationLong" value="100"/>
+<param name="psElongationOffset" value="100"/>
+<param name="mvStopFrame" value="1"/>
+<param name="mvCreamFrame" value="0"/>
+<param name="mlMinStopFrame" value="4mil"/>
+<param name="mlMaxStopFrame" value="4mil"/>
+<param name="mlMinCreamFrame" value="0mil"/>
+<param name="mlMaxCreamFrame" value="0mil"/>
+<param name="mlViaStopLimit" value="0mil"/>
+<param name="srRoundness" value="0"/>
+<param name="srMinRoundness" value="0mil"/>
+<param name="srMaxRoundness" value="0mil"/>
+<param name="slThermalIsolate" value="10mil"/>
+<param name="slThermalsForVias" value="0"/>
+<param name="dpMaxLengthDifference" value="10mm"/>
+<param name="dpGapFactor" value="2.5"/>
+<param name="checkGrid" value="0"/>
+<param name="checkAngle" value="0"/>
+<param name="checkFont" value="1"/>
+<param name="checkRestrict" value="1"/>
+<param name="useDiameter" value="13"/>
+<param name="maxErrors" value="999999"/>
+</designrules>
+<autorouter>
+<pass name="Default">
+<param name="RoutingGrid" value="50mil"/>
+<param name="tpViaShape" value="round"/>
+<param name="PrefDir.1" value="|"/>
+<param name="PrefDir.2" value="0"/>
+<param name="PrefDir.3" value="0"/>
+<param name="PrefDir.4" value="0"/>
+<param name="PrefDir.5" value="0"/>
+<param name="PrefDir.6" value="0"/>
+<param name="PrefDir.7" value="0"/>
+<param name="PrefDir.8" value="0"/>
+<param name="PrefDir.9" value="0"/>
+<param name="PrefDir.10" value="0"/>
+<param name="PrefDir.11" value="0"/>
+<param name="PrefDir.12" value="0"/>
+<param name="PrefDir.13" value="0"/>
+<param name="PrefDir.14" value="0"/>
+<param name="PrefDir.15" value="0"/>
+<param name="PrefDir.16" value="-"/>
+<param name="cfVia" value="8"/>
+<param name="cfNonPref" value="5"/>
+<param name="cfChangeDir" value="2"/>
+<param name="cfOrthStep" value="2"/>
+<param name="cfDiagStep" value="3"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="1"/>
+<param name="cfMalusStep" value="1"/>
+<param name="cfPadImpact" value="4"/>
+<param name="cfSmdImpact" value="4"/>
+<param name="cfBusImpact" value="0"/>
+<param name="cfHugging" value="3"/>
+<param name="cfAvoid" value="4"/>
+<param name="cfPolygon" value="10"/>
+<param name="cfBase.1" value="0"/>
+<param name="cfBase.2" value="1"/>
+<param name="cfBase.3" value="1"/>
+<param name="cfBase.4" value="1"/>
+<param name="cfBase.5" value="1"/>
+<param name="cfBase.6" value="1"/>
+<param name="cfBase.7" value="1"/>
+<param name="cfBase.8" value="1"/>
+<param name="cfBase.9" value="1"/>
+<param name="cfBase.10" value="1"/>
+<param name="cfBase.11" value="1"/>
+<param name="cfBase.12" value="1"/>
+<param name="cfBase.13" value="1"/>
+<param name="cfBase.14" value="1"/>
+<param name="cfBase.15" value="1"/>
+<param name="cfBase.16" value="0"/>
+<param name="mnVias" value="20"/>
+<param name="mnSegments" value="9999"/>
+<param name="mnExtdSteps" value="9999"/>
+<param name="mnRipupLevel" value="10"/>
+<param name="mnRipupSteps" value="100"/>
+<param name="mnRipupTotal" value="100"/>
+</pass>
+<pass name="Follow-me" refer="Default" active="yes">
+</pass>
+<pass name="Busses" refer="Default" active="yes">
+<param name="cfNonPref" value="4"/>
+<param name="cfBusImpact" value="4"/>
+<param name="cfHugging" value="0"/>
+<param name="mnVias" value="0"/>
+</pass>
+<pass name="Route" refer="Default" active="yes">
+</pass>
+<pass name="Optimize1" refer="Default" active="yes">
+<param name="cfVia" value="99"/>
+<param name="cfExtdStep" value="10"/>
+<param name="cfHugging" value="1"/>
+<param name="mnExtdSteps" value="1"/>
+<param name="mnRipupLevel" value="0"/>
+</pass>
+<pass name="Optimize2" refer="Optimize1" active="yes">
+<param name="cfNonPref" value="0"/>
+<param name="cfChangeDir" value="6"/>
+<param name="cfExtdStep" value="0"/>
+<param name="cfBonusStep" value="2"/>
+<param name="cfMalusStep" value="2"/>
+<param name="cfPadImpact" value="2"/>
+<param name="cfSmdImpact" value="2"/>
+<param name="cfHugging" value="0"/>
+</pass>
+<pass name="Optimize3" refer="Optimize2" active="yes">
+<param name="cfChangeDir" value="8"/>
+<param name="cfPadImpact" value="0"/>
+<param name="cfSmdImpact" value="0"/>
+</pass>
+<pass name="Optimize4" refer="Optimize3" active="yes">
+<param name="cfChangeDir" value="25"/>
+</pass>
+</autorouter>
+<elements>
+<element name="IC1" library="74xx-eu" package="SO16" value="74AC165D" x="64.77" y="60.325" rot="R270"/>
+<element name="IC2" library="74xx-eu" package="SO16" value="74HC595D" x="24.13" y="62.865" rot="R90"/>
+<element name="IC3" library="74xx-eu" package="SO16" value="74HC595D" x="64.77" y="44.45" rot="R270"/>
+<element name="IC4" library="74xx-eu" package="SO16" value="74HC595D" x="24.13" y="39.37" rot="R90"/>
+<element name="IC5" library="memory-idt" package="SO28-3" value="" x="44.45" y="46.99" rot="R90">
+<attribute name="OC_NEWARK" value="34M6449" x="44.45" y="46.99" size="1.778" layer="27" rot="R90" display="off"/>
+<attribute name="MPN" value="IDT71256SA20YG" x="44.45" y="46.99" size="1.778" layer="27" rot="R90" display="off"/>
+<attribute name="MF" value="" x="44.45" y="46.99" size="1.778" layer="27" rot="R90" display="off"/>
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+</signal>
+<signal name="D5">
+<contactref element="IC1" pad="4"/>
+<contactref element="IC2" pad="5"/>
+<contactref element="IC5" pad="17"/>
+<wire x1="27.2034" y1="63.5" x2="33.02" y2="63.5" width="0.4064" layer="1"/>
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+<via x="33.02" y="52.705" extent="1-16" drill="0.6" shape="square"/>
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+<wire x1="41.275" y1="60.96" x2="61.6966" y2="60.96" width="0.4064" layer="1"/>
+</signal>
+<signal name="D6">
+<contactref element="IC1" pad="5"/>
+<contactref element="IC2" pad="6"/>
+<contactref element="IC5" pad="18"/>
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+</signal>
+<signal name="D7">
+<contactref element="IC1" pad="6"/>
+<contactref element="IC2" pad="7"/>
+<contactref element="IC5" pad="19"/>
+<wire x1="27.2034" y1="66.04" x2="30.48" y2="66.04" width="0.4064" layer="1"/>
+<via x="30.48" y="66.04" extent="1-16" drill="0.6" shape="square"/>
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+<via x="30.48" y="50.165" extent="1-16" drill="0.6" shape="square"/>
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+<wire x1="42.545" y1="58.42" x2="61.6966" y2="58.42" width="0.4064" layer="1"/>
+</signal>
+<signal name="N$2">
+<contactref element="IC4" pad="9"/>
+<contactref element="IC2" pad="14"/>
+<wire x1="21.0566" y1="60.96" x2="19.05" y2="60.96" width="0.4064" layer="1"/>
+<via x="19.05" y="60.96" extent="1-16" drill="0.6" shape="square"/>
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+<wire x1="19.05" y1="43.815" x2="21.0566" y2="43.815" width="0.4064" layer="1"/>
+</signal>
+<signal name="N$3">
+<contactref element="IC2" pad="9"/>
+<contactref element="IC1" pad="10"/>
+<wire x1="21.0566" y1="67.31" x2="22.86" y2="67.31" width="0.4064" layer="1"/>
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+<wire x1="69.85" y1="57.15" x2="67.8434" y2="57.15" width="0.4064" layer="1"/>
+</signal>
+<signal name="D_IN">
+<contactref element="IC3" pad="14"/>
+</signal>
+<signal name="D_CLK">
+<contactref element="IC3" pad="11"/>
+<contactref element="IC4" pad="11"/>
+<contactref element="IC2" pad="11"/>
+<contactref element="IC1" pad="2"/>
+<wire x1="67.8434" y1="42.545" x2="61.6966" y2="63.5" width="0" layer="19" extent="1-1"/>
+<wire x1="21.0566" y1="64.77" x2="61.6966" y2="63.5" width="0" layer="19" extent="1-1"/>
+<wire x1="21.0566" y1="41.275" x2="21.0566" y2="64.77" width="0" layer="19" extent="1-1"/>
+</signal>
+<signal name="N$5">
+<contactref element="IC2" pad="12"/>
+<contactref element="IC4" pad="12"/>
+<contactref element="IC3" pad="12"/>
+<contactref element="IC1" pad="1"/>
+<wire x1="67.8434" y1="43.815" x2="61.6966" y2="64.77" width="0" layer="19" extent="1-1"/>
+<wire x1="21.0566" y1="63.5" x2="61.6966" y2="64.77" width="0" layer="19" extent="1-1"/>
+<wire x1="21.0566" y1="40.005" x2="21.0566" y2="63.5" width="0" layer="19" extent="1-1"/>
+</signal>
+</signals>
+</board>
+</drawing>
+</eagle>
diff --git a/hardware-v1/ram-ice.sch b/hardware-v1/ram-ice.sch
new file mode 100644
index 0000000..e06ad85
--- /dev/null
+++ b/hardware-v1/ram-ice.sch
@@ -0,0 +1,1228 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="6.4">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
+<grid distance="0.1" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.01" altunitdist="inch" altunit="inch"/>
+<layers>
+<layer number="1" name="Top" color="4" fill="1" visible="yes" active="no"/>
+<layer number="16" name="Bottom" color="1" fill="1" visible="yes" active="no"/>
+<layer number="17" name="Pads" color="2" fill="1" visible="yes" active="no"/>
+<layer number="18" name="Vias" color="2" fill="1" visible="yes" active="no"/>
+<layer number="19" name="Unrouted" color="6" fill="1" visible="yes" active="no"/>
+<layer number="20" name="Dimension" color="15" fill="1" visible="yes" active="no"/>
+<layer number="21" name="tPlace" color="7" fill="1" visible="yes" active="no"/>
+<layer number="22" name="bPlace" color="7" fill="1" visible="yes" active="no"/>
+<layer number="23" name="tOrigins" color="15" fill="1" visible="yes" active="no"/>
+<layer number="24" name="bOrigins" color="15" fill="1" visible="yes" active="no"/>
+<layer number="25" name="tNames" color="7" fill="1" visible="yes" active="no"/>
+<layer number="26" name="bNames" color="7" fill="1" visible="yes" active="no"/>
+<layer number="27" name="tValues" color="7" fill="1" visible="yes" active="no"/>
+<layer number="28" name="bValues" color="7" fill="1" visible="yes" active="no"/>
+<layer number="29" name="tStop" color="7" fill="3" visible="no" active="no"/>
+<layer number="30" name="bStop" color="7" fill="6" visible="no" active="no"/>
+<layer number="31" name="tCream" color="7" fill="4" visible="no" active="no"/>
+<layer number="32" name="bCream" color="7" fill="5" visible="no" active="no"/>
+<layer number="33" name="tFinish" color="6" fill="3" visible="no" active="no"/>
+<layer number="34" name="bFinish" color="6" fill="6" visible="no" active="no"/>
+<layer number="35" name="tGlue" color="7" fill="4" visible="no" active="no"/>
+<layer number="36" name="bGlue" color="7" fill="5" visible="no" active="no"/>
+<layer number="37" name="tTest" color="7" fill="1" visible="yes" active="no"/>
+<layer number="38" name="bTest" color="7" fill="1" visible="yes" active="no"/>
+<layer number="39" name="tKeepout" color="4" fill="11" visible="no" active="no"/>
+<layer number="40" name="bKeepout" color="1" fill="11" visible="no" active="no"/>
+<layer number="41" name="tRestrict" color="4" fill="10" visible="no" active="no"/>
+<layer number="42" name="bRestrict" color="1" fill="10" visible="no" active="no"/>
+<layer number="43" name="vRestrict" color="2" fill="10" visible="no" active="no"/>
+<layer number="44" name="Drills" color="7" fill="1" visible="no" active="no"/>
+<layer number="45" name="Holes" color="7" fill="1" visible="no" active="no"/>
+<layer number="46" name="Milling" color="3" fill="1" visible="yes" active="no"/>
+<layer number="47" name="Measures" color="7" fill="1" visible="yes" active="no"/>
+<layer number="48" name="Document" color="7" fill="1" visible="yes" active="no"/>
+<layer number="49" name="Reference" color="7" fill="1" visible="yes" active="no"/>
+<layer number="51" name="tDocu" color="7" fill="1" visible="yes" active="no"/>
+<layer number="52" name="bDocu" color="7" fill="1" visible="yes" active="no"/>
+<layer number="91" name="Nets" color="2" fill="1" visible="yes" active="yes"/>
+<layer number="92" name="Busses" color="1" fill="1" visible="yes" active="yes"/>
+<layer number="93" name="Pins" color="2" fill="1" visible="no" active="yes"/>
+<layer number="94" name="Symbols" color="4" fill="1" visible="yes" active="yes"/>
+<layer number="95" name="Names" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="96" name="Values" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="97" name="Info" color="7" fill="1" visible="yes" active="yes"/>
+<layer number="98" name="Guide" color="6" fill="1" visible="yes" active="yes"/>
+</layers>
+<schematic xreflabel="%F%N/%S.%C%R" xrefpart="/%S.%C%R">
+<libraries>
+<library name="74xx-eu">
+<description>&lt;b&gt;TTL Devices, 74xx Series with European Symbols&lt;/b&gt;&lt;p&gt;
+Based on the following sources:
+&lt;ul&gt;
+&lt;li&gt;Texas Instruments &lt;i&gt;TTL Data Book&lt;/i&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;Volume 1, 1996.
+&lt;li&gt;TTL Data Book, Volume 2 , 1993
+&lt;li&gt;National Seminconductor Databook 1990, ALS/LS Logic
+&lt;li&gt;ttl 74er digital data dictionary, ECA Electronic + Acustic GmbH, ISBN 3-88109-032-0
+&lt;li&gt;http://icmaster.com/ViewCompare.asp
+&lt;/ul&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL16">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt;</description>
+<wire x1="10.16" y1="2.921" x2="-10.16" y2="2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="10.16" y1="2.921" x2="10.16" y2="-2.921" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="2.921" x2="-10.16" y2="1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="-2.921" x2="-10.16" y2="-1.016" width="0.1524" layer="21"/>
+<wire x1="-10.16" y1="1.016" x2="-10.16" y2="-1.016" width="0.1524" layer="21" curve="-180"/>
+<pad name="1" x="-8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="6.35" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="8.89" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-3.81" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-1.27" y="-3.81" drill="0.8128" shape="long" rot="R90"/>
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+<pad name="9" x="8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="-1.27" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="-3.81" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="15" x="-6.35" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<pad name="16" x="-8.89" y="3.81" drill="0.8128" shape="long" rot="R90"/>
+<text x="-10.541" y="-2.921" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-7.493" y="-0.635" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="SO16">
+<description>&lt;b&gt;Small Outline package&lt;/b&gt; 150 mil</description>
+<wire x1="4.699" y1="1.9558" x2="-4.699" y2="1.9558" width="0.1524" layer="51"/>
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+<text x="-3.81" y="-0.762" size="1.27" layer="27" ratio="10">&gt;VALUE</text>
+<text x="-5.461" y="-1.905" size="1.27" layer="25" ratio="10" rot="R90">&gt;NAME</text>
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+<text x="-4.0051" y="6.065" size="1.778" layer="25">&gt;NAME</text>
+<text x="-3.9751" y="-7.5601" size="1.778" layer="27">&gt;VALUE</text>
+</package>
+</packages>
+<symbols>
+<symbol name="74165">
+<wire x1="-7.62" y1="-17.78" x2="7.62" y2="-17.78" width="0.4064" layer="94"/>
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+<text x="-7.62" y="18.415" size="1.778" layer="95" font="vector">&gt;NAME</text>
+<text x="-7.62" y="-20.32" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="SH/!LD" x="-12.7" y="-15.24" length="middle" direction="in"/>
+<pin name="CLK" x="-12.7" y="-10.16" length="middle" direction="in" function="clk"/>
+<pin name="E" x="-12.7" y="2.54" length="middle" direction="in"/>
+<pin name="F" x="-12.7" y="0" length="middle" direction="in"/>
+<pin name="G" x="-12.7" y="-2.54" length="middle" direction="in"/>
+<pin name="H" x="-12.7" y="-5.08" length="middle" direction="in"/>
+<pin name="!QH" x="12.7" y="5.08" length="middle" direction="out" rot="R180"/>
+<pin name="QH" x="12.7" y="12.7" length="middle" direction="out" rot="R180"/>
+<pin name="SER" x="-12.7" y="15.24" length="middle" direction="in"/>
+<pin name="A" x="-12.7" y="12.7" length="middle" direction="in"/>
+<pin name="B" x="-12.7" y="10.16" length="middle" direction="in"/>
+<pin name="C" x="-12.7" y="7.62" length="middle" direction="in"/>
+<pin name="D" x="-12.7" y="5.08" length="middle" direction="in"/>
+<pin name="INH" x="-12.7" y="-12.7" length="middle" direction="in" function="clk"/>
+</symbol>
+<symbol name="PWRN">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="2.54" size="1.27" layer="95" rot="R90">VCC</text>
+<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+</symbol>
+<symbol name="74595">
+<wire x1="-7.62" y1="-15.24" x2="7.62" y2="-15.24" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-15.24" x2="7.62" y2="12.7" width="0.4064" layer="94"/>
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+<wire x1="-7.62" y1="12.7" x2="-7.62" y2="-15.24" width="0.4064" layer="94"/>
+<text x="-7.62" y="13.335" size="1.778" layer="95" font="vector">&gt;NAME</text>
+<text x="-7.62" y="-17.78" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="QB" x="12.7" y="7.62" length="middle" direction="hiz" rot="R180"/>
+<pin name="QC" x="12.7" y="5.08" length="middle" direction="hiz" rot="R180"/>
+<pin name="QD" x="12.7" y="2.54" length="middle" direction="hiz" rot="R180"/>
+<pin name="QE" x="12.7" y="0" length="middle" direction="hiz" rot="R180"/>
+<pin name="QF" x="12.7" y="-2.54" length="middle" direction="hiz" rot="R180"/>
+<pin name="QG" x="12.7" y="-5.08" length="middle" direction="hiz" rot="R180"/>
+<pin name="QH" x="12.7" y="-7.62" length="middle" direction="hiz" rot="R180"/>
+<pin name="SCL" x="-12.7" y="2.54" length="middle" direction="in" function="dot"/>
+<pin name="SCK" x="-12.7" y="5.08" length="middle" direction="in" function="clk"/>
+<pin name="RCK" x="-12.7" y="-2.54" length="middle" direction="in" function="clk"/>
+<pin name="G" x="-12.7" y="-12.7" length="middle" direction="in" function="dot"/>
+<pin name="SER" x="-12.7" y="10.16" length="middle" direction="in"/>
+<pin name="QA" x="12.7" y="10.16" length="middle" direction="hiz" rot="R180"/>
+<pin name="QH*" x="12.7" y="-12.7" length="middle" direction="hiz" rot="R180"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="74*165" prefix="IC">
+<description>8-bit parallel load &lt;b&gt;SHIFT REGISTER&lt;/b&gt;</description>
+<gates>
+<gate name="A" symbol="74165" x="20.32" y="0"/>
+<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="N" package="DIL16">
+<connects>
+<connect gate="A" pin="!QH" pad="7"/>
+<connect gate="A" pin="A" pad="11"/>
+<connect gate="A" pin="B" pad="12"/>
+<connect gate="A" pin="C" pad="13"/>
+<connect gate="A" pin="CLK" pad="2"/>
+<connect gate="A" pin="D" pad="14"/>
+<connect gate="A" pin="E" pad="3"/>
+<connect gate="A" pin="F" pad="4"/>
+<connect gate="A" pin="G" pad="5"/>
+<connect gate="A" pin="H" pad="6"/>
+<connect gate="A" pin="INH" pad="15"/>
+<connect gate="A" pin="QH" pad="9"/>
+<connect gate="A" pin="SER" pad="10"/>
+<connect gate="A" pin="SH/!LD" pad="1"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
+</connects>
+<technologies>
+<technology name=""/>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="D" package="SO16">
+<connects>
+<connect gate="A" pin="!QH" pad="7"/>
+<connect gate="A" pin="A" pad="11"/>
+<connect gate="A" pin="B" pad="12"/>
+<connect gate="A" pin="C" pad="13"/>
+<connect gate="A" pin="CLK" pad="2"/>
+<connect gate="A" pin="D" pad="14"/>
+<connect gate="A" pin="E" pad="3"/>
+<connect gate="A" pin="F" pad="4"/>
+<connect gate="A" pin="G" pad="5"/>
+<connect gate="A" pin="H" pad="6"/>
+<connect gate="A" pin="INH" pad="15"/>
+<connect gate="A" pin="QH" pad="9"/>
+<connect gate="A" pin="SER" pad="10"/>
+<connect gate="A" pin="SH/!LD" pad="1"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
+</connects>
+<technologies>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="FK" package="LCC20">
+<connects>
+<connect gate="A" pin="!QH" pad="9"/>
+<connect gate="A" pin="A" pad="14"/>
+<connect gate="A" pin="B" pad="15"/>
+<connect gate="A" pin="C" pad="17"/>
+<connect gate="A" pin="CLK" pad="3"/>
+<connect gate="A" pin="D" pad="18"/>
+<connect gate="A" pin="E" pad="4"/>
+<connect gate="A" pin="F" pad="5"/>
+<connect gate="A" pin="G" pad="7"/>
+<connect gate="A" pin="H" pad="8"/>
+<connect gate="A" pin="INH" pad="19"/>
+<connect gate="A" pin="QH" pad="12"/>
+<connect gate="A" pin="SER" pad="13"/>
+<connect gate="A" pin="SH/!LD" pad="2"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="AC"/>
+<technology name="ACT"/>
+<technology name="HC"/>
+<technology name="LS"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="74*595" prefix="IC">
+<description>8-bit &lt;b&gt;SHIFT REGISTER&lt;/b&gt;, output latch</description>
+<gates>
+<gate name="A" symbol="74595" x="22.86" y="0"/>
+<gate name="P" symbol="PWRN" x="-5.08" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="N" package="DIL16">
+<connects>
+<connect gate="A" pin="G" pad="13"/>
+<connect gate="A" pin="QA" pad="15"/>
+<connect gate="A" pin="QB" pad="1"/>
+<connect gate="A" pin="QC" pad="2"/>
+<connect gate="A" pin="QD" pad="3"/>
+<connect gate="A" pin="QE" pad="4"/>
+<connect gate="A" pin="QF" pad="5"/>
+<connect gate="A" pin="QG" pad="6"/>
+<connect gate="A" pin="QH" pad="7"/>
+<connect gate="A" pin="QH*" pad="9"/>
+<connect gate="A" pin="RCK" pad="12"/>
+<connect gate="A" pin="SCK" pad="11"/>
+<connect gate="A" pin="SCL" pad="10"/>
+<connect gate="A" pin="SER" pad="14"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
+</connects>
+<technologies>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+<device name="D" package="SO16">
+<connects>
+<connect gate="A" pin="G" pad="13"/>
+<connect gate="A" pin="QA" pad="15"/>
+<connect gate="A" pin="QB" pad="1"/>
+<connect gate="A" pin="QC" pad="2"/>
+<connect gate="A" pin="QD" pad="3"/>
+<connect gate="A" pin="QE" pad="4"/>
+<connect gate="A" pin="QF" pad="5"/>
+<connect gate="A" pin="QG" pad="6"/>
+<connect gate="A" pin="QH" pad="7"/>
+<connect gate="A" pin="QH*" pad="9"/>
+<connect gate="A" pin="RCK" pad="12"/>
+<connect gate="A" pin="SCK" pad="11"/>
+<connect gate="A" pin="SCL" pad="10"/>
+<connect gate="A" pin="SER" pad="14"/>
+<connect gate="P" pin="GND" pad="8"/>
+<connect gate="P" pin="VCC" pad="16"/>
+</connects>
+<technologies>
+<technology name="HC"/>
+<technology name="HCT"/>
+</technologies>
+</device>
+<device name="FK" package="LCC20">
+<connects>
+<connect gate="A" pin="G" pad="17"/>
+<connect gate="A" pin="QA" pad="19"/>
+<connect gate="A" pin="QB" pad="2"/>
+<connect gate="A" pin="QC" pad="3"/>
+<connect gate="A" pin="QD" pad="4"/>
+<connect gate="A" pin="QE" pad="5"/>
+<connect gate="A" pin="QF" pad="7"/>
+<connect gate="A" pin="QG" pad="8"/>
+<connect gate="A" pin="QH" pad="9"/>
+<connect gate="A" pin="QH*" pad="12"/>
+<connect gate="A" pin="RCK" pad="15"/>
+<connect gate="A" pin="SCK" pad="14"/>
+<connect gate="A" pin="SCL" pad="13"/>
+<connect gate="A" pin="SER" pad="18"/>
+<connect gate="P" pin="GND" pad="10"/>
+<connect gate="P" pin="VCC" pad="20"/>
+</connects>
+<technologies>
+<technology name="HC"/>
+<technology name="HCT"/>
+<technology name="LS"/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="memory-idt">
+<description>&lt;b&gt;IDT Memories&lt;/b&gt;&lt;p&gt;
+Integrated Device Technology, Inc.&lt;p&gt;
+http://www.idt.com&lt;p&gt;
+&lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+<package name="DIL28-6">
+<description>&lt;b&gt;Dual In Line Package&lt;/b&gt; 0.6 inch</description>
+<wire x1="-17.653" y1="-1.27" x2="-17.653" y2="-6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="1.27" x2="-17.653" y2="-1.27" width="0.1524" layer="21" curve="-180"/>
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+<wire x1="-17.653" y1="6.604" x2="-17.653" y2="1.27" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="6.604" x2="17.653" y2="6.604" width="0.1524" layer="21"/>
+<wire x1="-17.653" y1="-6.604" x2="17.653" y2="-6.604" width="0.1524" layer="21"/>
+<pad name="1" x="-16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="2" x="-13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="3" x="-11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="4" x="-8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="5" x="-6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="6" x="-3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="7" x="-1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="8" x="1.27" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="9" x="3.81" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="10" x="6.35" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="11" x="8.89" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="12" x="11.43" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="13" x="13.97" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="14" x="16.51" y="-7.62" drill="0.8128" shape="long" rot="R90"/>
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+<pad name="17" x="11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="18" x="8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="19" x="6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="20" x="3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="21" x="1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="22" x="-1.27" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="23" x="-3.81" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="24" x="-6.35" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="25" x="-8.89" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="26" x="-11.43" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="27" x="-13.97" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<pad name="28" x="-16.51" y="7.62" drill="0.8128" shape="long" rot="R90"/>
+<text x="-17.78" y="-6.35" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-14.605" y="-0.9398" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+</package>
+<package name="SO28-3">
+<description>&lt;b&gt;Small Outline Package&lt;/b&gt;</description>
+<wire x1="-8.814" y1="-4.248" x2="8.839" y2="-4.248" width="0.1524" layer="21"/>
+<wire x1="8.839" y1="-4.248" x2="8.839" y2="4.248" width="0.1524" layer="21"/>
+<wire x1="8.839" y1="4.248" x2="-8.814" y2="4.248" width="0.1524" layer="21"/>
+<wire x1="-8.814" y1="4.248" x2="-8.814" y2="-4.248" width="0.1524" layer="21"/>
+<circle x="-7.874" y="-3.0988" radius="0.5334" width="0.1524" layer="21"/>
+<smd name="1" x="-8.255" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="2" x="-6.985" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="3" x="-5.715" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="4" x="-4.445" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="5" x="-3.175" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="6" x="-1.905" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="7" x="-0.635" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="8" x="0.635" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="9" x="1.905" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="10" x="3.175" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="20" x="1.905" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="19" x="3.175" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="18" x="4.445" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="17" x="5.715" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="16" x="6.985" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="15" x="8.255" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="14" x="8.255" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="13" x="6.985" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="12" x="5.715" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="11" x="4.445" y="-5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="21" x="0.635" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="22" x="-0.635" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="23" x="-1.905" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="24" x="-3.175" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="25" x="-4.445" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="26" x="-5.715" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="27" x="-6.985" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<smd name="28" x="-8.255" y="5.315" dx="0.762" dy="1.524" layer="1"/>
+<text x="-9.144" y="-4.318" size="1.778" layer="25" ratio="10" rot="R90">&gt;NAME</text>
+<text x="-7.874" y="-1.524" size="1.778" layer="27" ratio="10">&gt;VALUE</text>
+<rectangle x1="-8.509" y1="-5.7976" x2="-8.001" y2="-4.2736" layer="51"/>
+<rectangle x1="-7.239" y1="-5.7976" x2="-6.731" y2="-4.2736" layer="51"/>
+<rectangle x1="-5.969" y1="-5.7976" x2="-5.461" y2="-4.2736" layer="51"/>
+<rectangle x1="-4.699" y1="-5.7976" x2="-4.191" y2="-4.2736" layer="51"/>
+<rectangle x1="-3.429" y1="-5.7976" x2="-2.921" y2="-4.2736" layer="51"/>
+<rectangle x1="-2.159" y1="-5.7976" x2="-1.651" y2="-4.2736" layer="51"/>
+<rectangle x1="-0.889" y1="-5.7976" x2="-0.381" y2="-4.2736" layer="51"/>
+<rectangle x1="0.381" y1="-5.7976" x2="0.889" y2="-4.2736" layer="51"/>
+<rectangle x1="1.651" y1="-5.7976" x2="2.159" y2="-4.2736" layer="51"/>
+<rectangle x1="2.921" y1="-5.7976" x2="3.429" y2="-4.2736" layer="51"/>
+<rectangle x1="4.191" y1="-5.7976" x2="4.699" y2="-4.2736" layer="51"/>
+<rectangle x1="5.461" y1="-5.7976" x2="5.969" y2="-4.2736" layer="51"/>
+<rectangle x1="6.731" y1="-5.7976" x2="7.239" y2="-4.2736" layer="51"/>
+<rectangle x1="8.001" y1="-5.7976" x2="8.509" y2="-4.2736" layer="51"/>
+<rectangle x1="8.001" y1="4.2735" x2="8.509" y2="5.7975" layer="51"/>
+<rectangle x1="6.731" y1="4.2735" x2="7.239" y2="5.7975" layer="51"/>
+<rectangle x1="5.461" y1="4.2735" x2="5.969" y2="5.7975" layer="51"/>
+<rectangle x1="4.191" y1="4.2735" x2="4.699" y2="5.7975" layer="51"/>
+<rectangle x1="2.921" y1="4.2735" x2="3.429" y2="5.7975" layer="51"/>
+<rectangle x1="1.651" y1="4.2735" x2="2.159" y2="5.7975" layer="51"/>
+<rectangle x1="0.381" y1="4.2735" x2="0.889" y2="5.7975" layer="51"/>
+<rectangle x1="-0.889" y1="4.2735" x2="-0.381" y2="5.7975" layer="51"/>
+<rectangle x1="-2.159" y1="4.2735" x2="-1.651" y2="5.7975" layer="51"/>
+<rectangle x1="-3.429" y1="4.2735" x2="-2.921" y2="5.7975" layer="51"/>
+<rectangle x1="-4.699" y1="4.2735" x2="-4.191" y2="5.7975" layer="51"/>
+<rectangle x1="-5.969" y1="4.2735" x2="-5.461" y2="5.7975" layer="51"/>
+<rectangle x1="-7.239" y1="4.2735" x2="-6.731" y2="5.7975" layer="51"/>
+<rectangle x1="-8.509" y1="4.2735" x2="-8.001" y2="5.7975" layer="51"/>
+</package>
+</packages>
+<symbols>
+<symbol name="71256">
+<wire x1="-7.62" y1="-25.4" x2="7.62" y2="-25.4" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="-25.4" x2="7.62" y2="25.4" width="0.4064" layer="94"/>
+<wire x1="7.62" y1="25.4" x2="-7.62" y2="25.4" width="0.4064" layer="94"/>
+<wire x1="-7.62" y1="25.4" x2="-7.62" y2="-25.4" width="0.4064" layer="94"/>
+<text x="-7.62" y="26.035" size="1.778" layer="95">&gt;NAME</text>
+<text x="-7.62" y="-27.94" size="1.778" layer="96">&gt;VALUE</text>
+<pin name="A0" x="-12.7" y="22.86" length="middle" direction="in"/>
+<pin name="A1" x="-12.7" y="20.32" length="middle" direction="in"/>
+<pin name="A2" x="-12.7" y="17.78" length="middle" direction="in"/>
+<pin name="A3" x="-12.7" y="15.24" length="middle" direction="in"/>
+<pin name="A4" x="-12.7" y="12.7" length="middle" direction="in"/>
+<pin name="A5" x="-12.7" y="10.16" length="middle" direction="in"/>
+<pin name="A6" x="-12.7" y="7.62" length="middle" direction="in"/>
+<pin name="A7" x="-12.7" y="5.08" length="middle" direction="in"/>
+<pin name="A8" x="-12.7" y="2.54" length="middle" direction="in"/>
+<pin name="A9" x="-12.7" y="0" length="middle" direction="in"/>
+<pin name="A10" x="-12.7" y="-2.54" length="middle" direction="in"/>
+<pin name="!OE" x="-12.7" y="-17.78" length="middle" direction="in"/>
+<pin name="I/O5" x="12.7" y="12.7" length="middle" rot="R180"/>
+<pin name="I/O6" x="12.7" y="10.16" length="middle" rot="R180"/>
+<pin name="I/O7" x="12.7" y="7.62" length="middle" rot="R180"/>
+<pin name="I/O8" x="12.7" y="5.08" length="middle" rot="R180"/>
+<pin name="!WE" x="-12.7" y="-20.32" length="middle" direction="in"/>
+<pin name="!CS" x="-12.7" y="-22.86" length="middle" direction="in"/>
+<pin name="I/O1" x="12.7" y="22.86" length="middle" rot="R180"/>
+<pin name="I/O2" x="12.7" y="20.32" length="middle" rot="R180"/>
+<pin name="I/O3" x="12.7" y="17.78" length="middle" rot="R180"/>
+<pin name="I/O4" x="12.7" y="15.24" length="middle" rot="R180"/>
+<pin name="A11" x="-12.7" y="-5.08" length="middle" direction="in"/>
+<pin name="A12" x="-12.7" y="-7.62" length="middle" direction="in"/>
+<pin name="A13" x="-12.7" y="-10.16" length="middle" direction="in"/>
+<pin name="A14" x="-12.7" y="-12.7" length="middle" direction="in"/>
+</symbol>
+<symbol name="VCCGND">
+<text x="-0.635" y="-0.635" size="1.778" layer="95">&gt;NAME</text>
+<text x="1.905" y="-5.842" size="1.27" layer="95" rot="R90">GND</text>
+<text x="1.905" y="2.413" size="1.27" layer="95" rot="R90">VCC</text>
+<pin name="VCC" x="0" y="7.62" visible="pad" length="middle" direction="pwr" rot="R270"/>
+<pin name="GND" x="0" y="-7.62" visible="pad" length="middle" direction="pwr" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="71256P" prefix="IC" uservalue="yes">
+<description>&lt;b&gt;MEMORY&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="71256" x="0" y="0"/>
+<gate name="P" symbol="VCCGND" x="-25.4" y="0" addlevel="request"/>
+</gates>
+<devices>
+<device name="" package="DIL28-6">
+<connects>
+<connect gate="G$1" pin="!CS" pad="20"/>
+<connect gate="G$1" pin="!OE" pad="22"/>
+<connect gate="G$1" pin="!WE" pad="27"/>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="9"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="23"/>
+<connect gate="G$1" pin="A12" pad="2"/>
+<connect gate="G$1" pin="A13" pad="26"/>
+<connect gate="G$1" pin="A14" pad="1"/>
+<connect gate="G$1" pin="A2" pad="8"/>
+<connect gate="G$1" pin="A3" pad="7"/>
+<connect gate="G$1" pin="A4" pad="6"/>
+<connect gate="G$1" pin="A5" pad="5"/>
+<connect gate="G$1" pin="A6" pad="4"/>
+<connect gate="G$1" pin="A7" pad="3"/>
+<connect gate="G$1" pin="A8" pad="25"/>
+<connect gate="G$1" pin="A9" pad="24"/>
+<connect gate="G$1" pin="I/O1" pad="11"/>
+<connect gate="G$1" pin="I/O2" pad="12"/>
+<connect gate="G$1" pin="I/O3" pad="13"/>
+<connect gate="G$1" pin="I/O4" pad="15"/>
+<connect gate="G$1" pin="I/O5" pad="16"/>
+<connect gate="G$1" pin="I/O6" pad="17"/>
+<connect gate="G$1" pin="I/O7" pad="18"/>
+<connect gate="G$1" pin="I/O8" pad="19"/>
+<connect gate="P" pin="GND" pad="14"/>
+<connect gate="P" pin="VCC" pad="28"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="" constant="no"/>
+<attribute name="OC_FARNELL" value="unknown" constant="no"/>
+<attribute name="OC_NEWARK" value="unknown" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+<deviceset name="71256S" prefix="IC" uservalue="yes">
+<description>&lt;b&gt;MEMORY&lt;/b&gt;</description>
+<gates>
+<gate name="G$1" symbol="71256" x="0" y="0"/>
+<gate name="P" symbol="VCCGND" x="-22.86" y="2.54" addlevel="request"/>
+</gates>
+<devices>
+<device name="" package="SO28-3">
+<connects>
+<connect gate="G$1" pin="!CS" pad="20"/>
+<connect gate="G$1" pin="!OE" pad="22"/>
+<connect gate="G$1" pin="!WE" pad="27"/>
+<connect gate="G$1" pin="A0" pad="10"/>
+<connect gate="G$1" pin="A1" pad="9"/>
+<connect gate="G$1" pin="A10" pad="21"/>
+<connect gate="G$1" pin="A11" pad="23"/>
+<connect gate="G$1" pin="A12" pad="2"/>
+<connect gate="G$1" pin="A13" pad="26"/>
+<connect gate="G$1" pin="A14" pad="1"/>
+<connect gate="G$1" pin="A2" pad="8"/>
+<connect gate="G$1" pin="A3" pad="7"/>
+<connect gate="G$1" pin="A4" pad="6"/>
+<connect gate="G$1" pin="A5" pad="5"/>
+<connect gate="G$1" pin="A6" pad="4"/>
+<connect gate="G$1" pin="A7" pad="3"/>
+<connect gate="G$1" pin="A8" pad="25"/>
+<connect gate="G$1" pin="A9" pad="24"/>
+<connect gate="G$1" pin="I/O1" pad="11"/>
+<connect gate="G$1" pin="I/O2" pad="12"/>
+<connect gate="G$1" pin="I/O3" pad="13"/>
+<connect gate="G$1" pin="I/O4" pad="15"/>
+<connect gate="G$1" pin="I/O5" pad="16"/>
+<connect gate="G$1" pin="I/O6" pad="17"/>
+<connect gate="G$1" pin="I/O7" pad="18"/>
+<connect gate="G$1" pin="I/O8" pad="19"/>
+<connect gate="P" pin="GND" pad="14"/>
+<connect gate="P" pin="VCC" pad="28"/>
+</connects>
+<technologies>
+<technology name="">
+<attribute name="MF" value="" constant="no"/>
+<attribute name="MPN" value="IDT71256SA20YG" constant="no"/>
+<attribute name="OC_FARNELL" value="1218010" constant="no"/>
+<attribute name="OC_NEWARK" value="34M6449" constant="no"/>
+</technology>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+<library name="supply1">
+<description>&lt;b&gt;Supply Symbols&lt;/b&gt;&lt;p&gt;
+ GND, VCC, 0V, +5V, -5V, etc.&lt;p&gt;
+ Please keep in mind, that these devices are necessary for the
+ automatic wiring of the supply signals.&lt;p&gt;
+ The pin name defined in the symbol is identical to the net which is to be wired automatically.&lt;p&gt;
+ In this library the device names are the same as the pin names of the symbols, therefore the correct signal names appear next to the supply symbols in the schematic.&lt;p&gt;
+ &lt;author&gt;Created by librarian@cadsoft.de&lt;/author&gt;</description>
+<packages>
+</packages>
+<symbols>
+<symbol name="VCC">
+<wire x1="1.27" y1="-1.905" x2="0" y2="0" width="0.254" layer="94"/>
+<wire x1="0" y1="0" x2="-1.27" y2="-1.905" width="0.254" layer="94"/>
+<text x="-2.54" y="-2.54" size="1.778" layer="96" rot="R90">&gt;VALUE</text>
+<pin name="VCC" x="0" y="-2.54" visible="off" length="short" direction="sup" rot="R90"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="VCC" prefix="P+">
+<description>&lt;b&gt;SUPPLY SYMBOL&lt;/b&gt;</description>
+<gates>
+<gate name="VCC" symbol="VCC" x="0" y="0"/>
+</gates>
+<devices>
+<device name="">
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</libraries>
+<attributes>
+</attributes>
+<variantdefs>
+</variantdefs>
+<classes>
+<class number="0" name="default" width="0" drill="0">
+</class>
+</classes>
+<parts>
+<part name="IC1" library="74xx-eu" deviceset="74*165" device="D" technology="AC"/>
+<part name="IC2" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/>
+<part name="IC3" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/>
+<part name="IC4" library="74xx-eu" deviceset="74*595" device="D" technology="HC"/>
+<part name="IC5" library="memory-idt" deviceset="71256S" device=""/>
+<part name="P+1" library="supply1" deviceset="VCC" device=""/>
+<part name="IC6" library="memory-idt" deviceset="71256P" device=""/>
+</parts>
+<sheets>
+<sheet>
+<plain>
+</plain>
+<instances>
+<instance part="IC1" gate="A" x="162.56" y="83.82"/>
+<instance part="IC2" gate="A" x="162.56" y="40.64" rot="R180"/>
+<instance part="IC3" gate="A" x="45.72" y="88.9"/>
+<instance part="IC4" gate="A" x="45.72" y="45.72"/>
+<instance part="IC5" gate="G$1" x="101.6" y="55.88"/>
+<instance part="P+1" gate="VCC" x="27.94" y="109.22"/>
+<instance part="IC6" gate="G$1" x="233.68" y="58.42"/>
+</instances>
+<busses>
+<bus name="A[0..7]">
+<segment>
+<wire x1="63.5" y1="99.06" x2="63.5" y2="81.28" width="0.762" layer="92"/>
+<wire x1="63.5" y1="81.28" x2="81.28" y2="81.28" width="0.762" layer="92"/>
+<wire x1="81.28" y1="81.28" x2="81.28" y2="60.96" width="0.762" layer="92"/>
+</segment>
+</bus>
+<bus name="A[8..14]">
+<segment>
+<wire x1="81.28" y1="58.42" x2="81.28" y2="35.56" width="0.762" layer="92"/>
+<wire x1="81.28" y1="35.56" x2="63.5" y2="35.56" width="0.762" layer="92"/>
+<wire x1="63.5" y1="35.56" x2="63.5" y2="55.88" width="0.762" layer="92"/>
+</segment>
+</bus>
+<bus name="D[0..7]">
+<segment>
+<wire x1="134.62" y1="96.52" x2="134.62" y2="78.74" width="0.762" layer="92"/>
+<wire x1="134.62" y1="78.74" x2="134.62" y2="30.48" width="0.762" layer="92"/>
+<wire x1="134.62" y1="78.74" x2="121.92" y2="78.74" width="0.762" layer="92"/>
+<wire x1="121.92" y1="78.74" x2="121.92" y2="60.96" width="0.762" layer="92"/>
+</segment>
+</bus>
+</busses>
+<nets>
+<net name="A1" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QB"/>
+<wire x1="58.42" y1="96.52" x2="63.5" y2="96.52" width="0.1524" layer="91"/>
+<label x="58.42" y="96.52" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A1"/>
+<wire x1="81.28" y1="76.2" x2="88.9" y2="76.2" width="0.1524" layer="91"/>
+<label x="88.9" y="76.2" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A0" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QA"/>
+<wire x1="58.42" y1="99.06" x2="63.5" y2="99.06" width="0.1524" layer="91"/>
+<label x="58.42" y="99.06" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A0"/>
+<wire x1="81.28" y1="78.74" x2="88.9" y2="78.74" width="0.1524" layer="91"/>
+<label x="88.9" y="78.74" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A3" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QD"/>
+<wire x1="63.5" y1="91.44" x2="58.42" y2="91.44" width="0.1524" layer="91"/>
+<label x="58.42" y="91.44" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A3"/>
+<wire x1="81.28" y1="71.12" x2="88.9" y2="71.12" width="0.1524" layer="91"/>
+<label x="88.9" y="71.12" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A2" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QC"/>
+<wire x1="63.5" y1="93.98" x2="58.42" y2="93.98" width="0.1524" layer="91"/>
+<label x="58.42" y="93.98" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A2"/>
+<wire x1="81.28" y1="73.66" x2="88.9" y2="73.66" width="0.1524" layer="91"/>
+<label x="88.9" y="73.66" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A4" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QE"/>
+<wire x1="63.5" y1="88.9" x2="58.42" y2="88.9" width="0.1524" layer="91"/>
+<label x="58.42" y="88.9" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A4"/>
+<wire x1="88.9" y1="68.58" x2="81.28" y2="68.58" width="0.1524" layer="91"/>
+<label x="88.9" y="68.58" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A5" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QF"/>
+<wire x1="63.5" y1="86.36" x2="58.42" y2="86.36" width="0.1524" layer="91"/>
+<label x="58.42" y="86.36" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A5"/>
+<wire x1="88.9" y1="66.04" x2="81.28" y2="66.04" width="0.1524" layer="91"/>
+<label x="88.9" y="66.04" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A6" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QG"/>
+<wire x1="63.5" y1="83.82" x2="58.42" y2="83.82" width="0.1524" layer="91"/>
+<label x="58.42" y="83.82" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A6"/>
+<wire x1="88.9" y1="63.5" x2="81.28" y2="63.5" width="0.1524" layer="91"/>
+<label x="88.9" y="63.5" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A7" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QH"/>
+<wire x1="63.5" y1="81.28" x2="58.42" y2="81.28" width="0.1524" layer="91"/>
+<label x="58.42" y="81.28" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A7"/>
+<wire x1="88.9" y1="60.96" x2="81.28" y2="60.96" width="0.1524" layer="91"/>
+<label x="88.9" y="60.96" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A8" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QA"/>
+<wire x1="58.42" y1="55.88" x2="63.5" y2="55.88" width="0.1524" layer="91"/>
+<label x="58.42" y="55.88" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A8"/>
+<wire x1="88.9" y1="58.42" x2="81.28" y2="58.42" width="0.1524" layer="91"/>
+<label x="88.9" y="58.42" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A9" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QB"/>
+<wire x1="58.42" y1="53.34" x2="63.5" y2="53.34" width="0.1524" layer="91"/>
+<label x="58.42" y="53.34" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A9"/>
+<wire x1="88.9" y1="55.88" x2="81.28" y2="55.88" width="0.1524" layer="91"/>
+<label x="88.9" y="55.88" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A10" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QC"/>
+<wire x1="58.42" y1="50.8" x2="63.5" y2="50.8" width="0.1524" layer="91"/>
+<label x="58.42" y="50.8" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A10"/>
+<wire x1="88.9" y1="53.34" x2="81.28" y2="53.34" width="0.1524" layer="91"/>
+<label x="88.9" y="53.34" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A11" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QD"/>
+<wire x1="58.42" y1="48.26" x2="63.5" y2="48.26" width="0.1524" layer="91"/>
+<label x="58.42" y="48.26" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A11"/>
+<wire x1="88.9" y1="50.8" x2="81.28" y2="50.8" width="0.1524" layer="91"/>
+<label x="88.9" y="50.8" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A12" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QE"/>
+<wire x1="58.42" y1="45.72" x2="63.5" y2="45.72" width="0.1524" layer="91"/>
+<label x="58.42" y="45.72" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A12"/>
+<wire x1="88.9" y1="48.26" x2="81.28" y2="48.26" width="0.1524" layer="91"/>
+<label x="88.9" y="48.26" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A13" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QF"/>
+<wire x1="58.42" y1="43.18" x2="63.5" y2="43.18" width="0.1524" layer="91"/>
+<label x="58.42" y="43.18" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A13"/>
+<wire x1="81.28" y1="45.72" x2="88.9" y2="45.72" width="0.1524" layer="91"/>
+<label x="88.9" y="45.72" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="A14" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QG"/>
+<wire x1="58.42" y1="40.64" x2="63.5" y2="40.64" width="0.1524" layer="91"/>
+<label x="58.42" y="40.64" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="A14"/>
+<wire x1="88.9" y1="43.18" x2="81.28" y2="43.18" width="0.1524" layer="91"/>
+<label x="88.9" y="43.18" size="1.778" layer="95" rot="MR0"/>
+</segment>
+</net>
+<net name="N$1" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="QH*"/>
+<wire x1="58.42" y1="76.2" x2="58.42" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="58.42" y1="66.04" x2="30.48" y2="66.04" width="0.1524" layer="91"/>
+<wire x1="30.48" y1="66.04" x2="30.48" y2="55.88" width="0.1524" layer="91"/>
+<pinref part="IC4" gate="A" pin="SER"/>
+<wire x1="30.48" y1="55.88" x2="33.02" y2="55.88" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="A_EN" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="G"/>
+<wire x1="33.02" y1="76.2" x2="22.86" y2="76.2" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="76.2" x2="22.86" y2="33.02" width="0.1524" layer="91"/>
+<pinref part="IC4" gate="A" pin="G"/>
+<wire x1="22.86" y1="33.02" x2="22.86" y2="25.4" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="33.02" x2="22.86" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="22.86" y1="25.4" x2="5.08" y2="25.4" width="0.1524" layer="91"/>
+<label x="5.08" y="27.94" size="1.778" layer="95"/>
+<junction x="22.86" y="33.02"/>
+</segment>
+</net>
+<net name="D0" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="A"/>
+<wire x1="134.62" y1="96.52" x2="149.86" y2="96.52" width="0.1524" layer="91"/>
+<label x="137.16" y="96.52" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QA"/>
+<wire x1="134.62" y1="30.48" x2="149.86" y2="30.48" width="0.1524" layer="91"/>
+<label x="137.16" y="30.48" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O1"/>
+<wire x1="114.3" y1="78.74" x2="121.92" y2="78.74" width="0.1524" layer="91"/>
+<label x="116.84" y="78.74" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D1" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="B"/>
+<wire x1="134.62" y1="93.98" x2="149.86" y2="93.98" width="0.1524" layer="91"/>
+<label x="137.16" y="93.98" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QB"/>
+<wire x1="134.62" y1="33.02" x2="149.86" y2="33.02" width="0.1524" layer="91"/>
+<label x="137.16" y="33.02" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O2"/>
+<wire x1="114.3" y1="76.2" x2="121.92" y2="76.2" width="0.1524" layer="91"/>
+<label x="116.84" y="76.2" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D2" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="C"/>
+<wire x1="134.62" y1="91.44" x2="149.86" y2="91.44" width="0.1524" layer="91"/>
+<label x="137.16" y="91.44" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QC"/>
+<wire x1="134.62" y1="35.56" x2="149.86" y2="35.56" width="0.1524" layer="91"/>
+<label x="137.16" y="35.56" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O3"/>
+<wire x1="114.3" y1="73.66" x2="121.92" y2="73.66" width="0.1524" layer="91"/>
+<label x="116.84" y="73.66" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D3" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="D"/>
+<wire x1="134.62" y1="88.9" x2="149.86" y2="88.9" width="0.1524" layer="91"/>
+<label x="137.16" y="88.9" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QD"/>
+<wire x1="134.62" y1="38.1" x2="149.86" y2="38.1" width="0.1524" layer="91"/>
+<label x="137.16" y="38.1" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O4"/>
+<wire x1="121.92" y1="71.12" x2="114.3" y2="71.12" width="0.1524" layer="91"/>
+<label x="116.84" y="71.12" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D4" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="E"/>
+<wire x1="134.62" y1="86.36" x2="149.86" y2="86.36" width="0.1524" layer="91"/>
+<label x="137.16" y="86.36" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QE"/>
+<wire x1="134.62" y1="40.64" x2="149.86" y2="40.64" width="0.1524" layer="91"/>
+<label x="137.16" y="40.64" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O5"/>
+<wire x1="121.92" y1="68.58" x2="114.3" y2="68.58" width="0.1524" layer="91"/>
+<label x="116.84" y="68.58" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D5" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="F"/>
+<wire x1="134.62" y1="83.82" x2="149.86" y2="83.82" width="0.1524" layer="91"/>
+<label x="137.16" y="83.82" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QF"/>
+<wire x1="134.62" y1="43.18" x2="149.86" y2="43.18" width="0.1524" layer="91"/>
+<label x="137.16" y="43.18" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O6"/>
+<wire x1="114.3" y1="66.04" x2="121.92" y2="66.04" width="0.1524" layer="91"/>
+<label x="116.84" y="66.04" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D6" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="G"/>
+<wire x1="134.62" y1="81.28" x2="149.86" y2="81.28" width="0.1524" layer="91"/>
+<label x="137.16" y="81.28" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QG"/>
+<wire x1="134.62" y1="45.72" x2="149.86" y2="45.72" width="0.1524" layer="91"/>
+<label x="137.16" y="45.72" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O7"/>
+<wire x1="114.3" y1="63.5" x2="121.92" y2="63.5" width="0.1524" layer="91"/>
+<label x="116.84" y="63.5" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D7" class="0">
+<segment>
+<pinref part="IC1" gate="A" pin="H"/>
+<wire x1="134.62" y1="78.74" x2="149.86" y2="78.74" width="0.1524" layer="91"/>
+<label x="137.16" y="78.74" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC2" gate="A" pin="QH"/>
+<wire x1="134.62" y1="48.26" x2="149.86" y2="48.26" width="0.1524" layer="91"/>
+<label x="137.16" y="48.26" size="1.778" layer="95"/>
+</segment>
+<segment>
+<pinref part="IC5" gate="G$1" pin="I/O8"/>
+<wire x1="114.3" y1="60.96" x2="121.92" y2="60.96" width="0.1524" layer="91"/>
+<label x="116.84" y="60.96" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="N$2" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="QH*"/>
+<wire x1="58.42" y1="33.02" x2="60.96" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="33.02" x2="60.96" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="60.96" y1="15.24" x2="180.34" y2="15.24" width="0.1524" layer="91"/>
+<wire x1="180.34" y1="15.24" x2="180.34" y2="30.48" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="A" pin="SER"/>
+<wire x1="180.34" y1="30.48" x2="175.26" y2="30.48" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="N$3" class="0">
+<segment>
+<pinref part="IC2" gate="A" pin="QH*"/>
+<wire x1="149.86" y1="53.34" x2="142.24" y2="53.34" width="0.1524" layer="91"/>
+<wire x1="142.24" y1="53.34" x2="142.24" y2="99.06" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="A" pin="SER"/>
+<wire x1="142.24" y1="99.06" x2="149.86" y2="99.06" width="0.1524" layer="91"/>
+</segment>
+</net>
+<net name="D_IN" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="SER"/>
+<wire x1="33.02" y1="99.06" x2="20.32" y2="99.06" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="99.06" x2="20.32" y2="33.02" width="0.1524" layer="91"/>
+<wire x1="20.32" y1="33.02" x2="5.08" y2="33.02" width="0.1524" layer="91"/>
+<label x="5.08" y="35.56" size="1.778" layer="95"/>
+</segment>
+</net>
+<net name="D_CLK" class="0">
+<segment>
+<pinref part="IC3" gate="A" pin="SCK"/>
+<wire x1="33.02" y1="93.98" x2="17.78" y2="93.98" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="93.98" x2="17.78" y2="50.8" width="0.1524" layer="91"/>
+<pinref part="IC4" gate="A" pin="SCK"/>
+<wire x1="17.78" y1="50.8" x2="33.02" y2="50.8" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="50.8" x2="17.78" y2="40.64" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="40.64" x2="5.08" y2="40.64" width="0.1524" layer="91"/>
+<label x="5.08" y="43.18" size="1.778" layer="95"/>
+<wire x1="17.78" y1="40.64" x2="17.78" y2="7.62" width="0.1524" layer="91"/>
+<wire x1="17.78" y1="7.62" x2="187.96" y2="7.62" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="7.62" x2="187.96" y2="35.56" width="0.1524" layer="91"/>
+<pinref part="IC2" gate="A" pin="SCK"/>
+<wire x1="175.26" y1="35.56" x2="187.96" y2="35.56" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="35.56" x2="187.96" y2="60.96" width="0.1524" layer="91"/>
+<wire x1="187.96" y1="60.96" x2="144.78" y2="60.96" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="A" pin="CLK"/>
+<wire x1="149.86" y1="73.66" x2="144.78" y2="73.66" width="0.1524" layer="91"/>
+<wire x1="144.78" y1="73.66" x2="144.78" y2="60.96" width="0.1524" layer="91"/>
+<junction x="17.78" y="40.64"/>
+<junction x="187.96" y="35.56"/>
+</segment>
+</net>
+<net name="N$5" class="0">
+<segment>
+<pinref part="IC2" gate="A" pin="RCK"/>
+<wire x1="175.26" y1="43.18" x2="185.42" y2="43.18" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="43.18" x2="185.42" y2="10.16" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="10.16" x2="25.4" y2="10.16" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="10.16" x2="25.4" y2="43.18" width="0.1524" layer="91"/>
+<pinref part="IC4" gate="A" pin="RCK"/>
+<wire x1="33.02" y1="43.18" x2="25.4" y2="43.18" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="RCK"/>
+<wire x1="33.02" y1="86.36" x2="25.4" y2="86.36" width="0.1524" layer="91"/>
+<wire x1="25.4" y1="86.36" x2="25.4" y2="43.18" width="0.1524" layer="91"/>
+<pinref part="IC1" gate="A" pin="SH/!LD"/>
+<wire x1="149.86" y1="68.58" x2="147.32" y2="68.58" width="0.1524" layer="91"/>
+<wire x1="147.32" y1="68.58" x2="147.32" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="147.32" y1="63.5" x2="185.42" y2="63.5" width="0.1524" layer="91"/>
+<wire x1="185.42" y1="63.5" x2="185.42" y2="43.18" width="0.1524" layer="91"/>
+<junction x="25.4" y="43.18"/>
+<junction x="185.42" y="43.18"/>
+</segment>
+</net>
+<net name="VCC" class="0">
+<segment>
+<pinref part="IC4" gate="A" pin="SCL"/>
+<wire x1="33.02" y1="48.26" x2="27.94" y2="48.26" width="0.1524" layer="91"/>
+<wire x1="27.94" y1="48.26" x2="27.94" y2="91.44" width="0.1524" layer="91"/>
+<pinref part="IC3" gate="A" pin="SCL"/>
+<wire x1="27.94" y1="91.44" x2="27.94" y2="106.68" width="0.1524" layer="91"/>
+<wire x1="33.02" y1="91.44" x2="27.94" y2="91.44" width="0.1524" layer="91"/>
+<junction x="27.94" y="91.44"/>
+<pinref part="P+1" gate="VCC" pin="VCC"/>
+</segment>
+</net>
+</nets>
+</sheet>
+</sheets>
+</schematic>
+</drawing>
+</eagle>
diff --git a/hardware-v1/untitled.pro b/hardware-v1/untitled.pro
new file mode 100644
index 0000000..d77689b
--- /dev/null
+++ b/hardware-v1/untitled.pro
@@ -0,0 +1,25 @@
+EAGLE AutoRouter Statistics:
+
+Job           : /home/trygvis/dev/io.trygvis/2013/02/ram-ice/untitled.brd
+
+Start at      : 01:56:21 (2/10/13)
+End at        : 01:56:21 (2/10/13)
+Elapsed time  : 00:00:00
+
+Signals       :    30   RoutingGrid: 50 mil  Layers: 2
+Connections   :    43   predefined:  0 ( 0 Vias )
+
+Router memory :   24708
+
+Passname          :    Busses     Route Optimize1 Optimize2 Optimize3 Optimize4
+
+Time per pass     :  00:00:00  00:00:00  00:00:00  00:00:00  00:00:00  00:00:00
+Number of Ripups  :         0         0         0         0         0         0
+max. Level        :         0         0         0         0         0         0
+max. Total        :         0         0         0         0         0         0
+
+Routed            :         0         0         0         0         0         0
+Vias              :         0         0         0         0         0         0
+Resolution        :     0.0 %     0.0 %     0.0 %     0.0 %     0.0 %     0.0 %
+
+Final             : 0.0% finished
-- 
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