From 6c56d89c8db4830418bdd27d5c775a77d0ab462b Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Sun, 10 Feb 2013 16:26:03 +0100 Subject: wip --- vhdl/ice.vhd | 80 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 vhdl/ice.vhd (limited to 'vhdl/ice.vhd') diff --git a/vhdl/ice.vhd b/vhdl/ice.vhd new file mode 100644 index 0000000..22e1f51 --- /dev/null +++ b/vhdl/ice.vhd @@ -0,0 +1,80 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + +library fmf; +use fmf.std595; + +use work.all; + +entity ice is + port ( + bit_in : in std_logic; + bit_out : out std_logic; + bit_clk : in std_logic; + byte_clk : in std_logic; + a_oe : in std_logic; + d_oe : in std_logic; + + ah : out std_logic_vector(7 downto 0); + al : out std_logic_vector(7 downto 0); + d_out : out std_logic_vector(7 downto 0) + ); +end; + +architecture behave of ice is + signal ah_out : std_logic; + signal al_out : std_logic; + signal d_out_out : std_logic; +begin + ah_buf : entity fmf.std595(vhdl_behavioral) port map( + ser => bit_in, + qhser => ah_out, + sck => bit_clk, + rck => byte_clk, + gneg => a_oe, + qa => ah(0), + qb => ah(1), + qc => ah(2), + qd => ah(3), + qe => ah(4), + qf => ah(5), + qg => ah(6), + qh => ah(7), + SCLRNeg => '1' + ); + + al_buf : entity fmf.std595(vhdl_behavioral) port map( + ser => ah_out, + qhser => al_out, + sck => bit_clk, + rck => byte_clk, + gneg => a_oe, + qa => al(0), + qb => al(1), + qc => al(2), + qd => al(3), + qe => al(4), + qf => al(5), + qg => al(6), + qh => al(7), + SCLRNeg => '1' + ); + + d_out_buf : entity fmf.std595(vhdl_behavioral) port map( + ser => al_out, + qhser => d_out_out, + sck => bit_clk, + rck => byte_clk, + gneg => d_oe, + qa => d_out(0), + qb => d_out(1), + qc => d_out(2), + qd => d_out(3), + qe => d_out(4), + qf => d_out(5), + qg => d_out(6), + qh => d_out(7), + SCLRNeg => '1' + ); +end; -- cgit v1.2.3