From ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4 Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Sun, 17 Feb 2013 12:30:14 +0100
Subject: o Using a bus for the memory input too. o Adding a test case for
 reading data from RAM.

---
 vhdl/ice.vhd | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

(limited to 'vhdl/ice.vhd')

diff --git a/vhdl/ice.vhd b/vhdl/ice.vhd
index 8cbff92..5f0329e 100644
--- a/vhdl/ice.vhd
+++ b/vhdl/ice.vhd
@@ -7,9 +7,7 @@ entity ice is
   port (
     mcu_in              : in mcu_in;
     bit_out             : out std_logic;
-    oe                  : in std_logic;
-    ce                  : in std_logic;
-    we                  : in std_logic
+    ram_in              : in ram_in
   );
 end ice;
 
@@ -25,8 +23,7 @@ begin
     bit_out,
     ah,
     al,
-    d,          -- d_out,
-    d           -- d_in
+    d
   );
 
   address : ram_address <= ah(14 downto 8) & al;
@@ -34,9 +31,9 @@ begin
   ram : entity work.as7c256a port map(
     address => ram_address,
     dataio => d,
-    oe_bar => oe,
-    ce_bar => ce,
-    we_bar => we
+    oe_bar => ram_in.oe,
+    ce_bar => ram_in.ce,
+    we_bar => ram_in.we
   );
 
 end;
-- 
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