From ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4 Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Sun, 17 Feb 2013 12:30:14 +0100 Subject: o Using a bus for the memory input too. o Adding a test case for reading data from RAM. --- vhdl/ice_tb.vhd | 17 ++++++++++++----- 1 file changed, 12 insertions(+), 5 deletions(-) (limited to 'vhdl/ice_tb.vhd') diff --git a/vhdl/ice_tb.vhd b/vhdl/ice_tb.vhd index dae94f4..c442f41 100644 --- a/vhdl/ice_tb.vhd +++ b/vhdl/ice_tb.vhd @@ -9,19 +9,26 @@ end; architecture behavior of ice_tb is signal mcu_in : mcu_in; signal bit_out : std_logic; - signal oe : std_logic := disable; - signal ce : std_logic := enable; - signal we : std_logic := disable; + signal ram_in : ram_in; + signal data : std_logic_vector(7 downto 0); begin ice : entity work.ice port map( - mcu_in, bit_out, oe, ce, we + mcu_in, bit_out, ram_in ); stimulus : process begin mcu_in <= mcu_in_initial; + mcu_in.a_oe <= enable; + ram_in <= ram_in_initial; + + ram_in.ce <= enable; + + write_ram(mcu_in, ram_in, "10100101", "1111000011110000"); + write_ram(mcu_in, ram_in, "01011010", "0000111100001111"); + + read_ram(mcu_in, ram_in, bit_out, data, "1111000011110000"); - write_ram(mcu_in, we, "10100101", "0000000000000001"); wait; end process; -- cgit v1.2.3