From ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4 Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Sun, 17 Feb 2013 12:30:14 +0100
Subject: o Using a bus for the memory input too. o Adding a test case for
 reading data from RAM.

---
 vhdl/mcu.vhd | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 53 insertions(+), 7 deletions(-)

(limited to 'vhdl/mcu.vhd')

diff --git a/vhdl/mcu.vhd b/vhdl/mcu.vhd
index e20f4f6..7cf273b 100644
--- a/vhdl/mcu.vhd
+++ b/vhdl/mcu.vhd
@@ -4,8 +4,6 @@ use ieee.std_logic_1164.all;
 library ieee_proposed;
 use ieee_proposed.std_logic_1164_additions.all;
 
--- use work.mcu.all;
-
 package mcu is
 
   type mcu_in is record
@@ -23,6 +21,12 @@ package mcu is
     d_oe                : std_logic; 
   end record;
 
+  type ram_in is record
+    oe                  : std_logic;
+    ce                  : std_logic;
+    we                  : std_logic;
+  end record;
+
   procedure byte_out(
     signal mcu_in       : out mcu_in;
     byte                : in std_logic_vector(7 downto 0)
@@ -36,11 +40,19 @@ package mcu is
 
   procedure write_ram(
     signal mcu_in       : out mcu_in;
-    signal we           : out std_logic;
+    signal ram_in       : out ram_in;
     data                : in std_logic_vector(7 downto 0);
     address             : in std_logic_vector(15 downto 0)
   );
 
+  procedure read_ram(
+    signal mcu_in       : out mcu_in;
+    signal ram_in       : out ram_in;
+    signal bit_out      : in std_logic;
+    signal data         : inout std_logic_vector(7 downto 0);
+    address             : in std_logic_vector(15 downto 0)
+  );
+
   constant tClk         : time :=  100 ns;
   constant disable      : std_logic := '1';
   constant enable       : std_logic := '0';
@@ -53,6 +65,12 @@ package mcu is
     a_oe => '1',
     d_oe => '1'
   );
+  
+  constant ram_in_initial : ram_in := (
+    oe => '1',
+    ce => '1',
+    we => '1'
+  );
 
 end mcu;
 
@@ -95,11 +113,11 @@ package body mcu is
 
   procedure write_ram(
     signal mcu_in       : out mcu_in;
-    signal we           : out std_logic;
+    signal ram_in       : out ram_in;
     data                : in std_logic_vector(7 downto 0);
     address             : in std_logic_vector(15 downto 0)) is
   begin
-    report "write_ram: " & to_string(data);
+    report "write_ram: " & to_string(address) & "=" & to_string(data);
 
     -- TODO: busreq + wait for busack
     byte_out(mcu_in, data);
@@ -114,11 +132,39 @@ package body mcu is
     -- Enable A and D outputs
     mcu_in.a_oe <= enable;
     mcu_in.d_oe <= enable;
-    we <= enable;
+    ram_in.we <= enable;
+
+    wait for tClk;
+
+    ram_in.we <= disable;
+    mcu_in.d_oe <= disable;
+  end;
+
+  procedure read_ram(
+    signal mcu_in       : out mcu_in;
+    signal ram_in       : out ram_in;
+    signal bit_out      : in std_logic;
+    signal data         : inout std_logic_vector(7 downto 0);
+    address             : in std_logic_vector(15 downto 0)) is
+  begin
+    -- TODO: busreq + wait for busack
+    byte_out(mcu_in, "00000000");
+    byte_out(mcu_in, address(7 downto 0));
+    byte_out(mcu_in, address(15 downto 8));
 
+    mcu_in.byte_out_clk <= '0';
+    ram_in.oe <= enable;
     wait for tClk;
 
-    we <= disable;
+    -- Clock the data out on the A and D busses
+    mcu_in.byte_out_clk <= '1';
+    wait for tClk;
+
+    byte_in(mcu_in, bit_out, data);
+
+    ram_in.oe <= disable;
+
+    report "read_ram: " & to_string(address) & "=" & to_string(data);
   end;
 
 end mcu;
-- 
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