From ee6e3ba807ce4d93988eb83b29b9af22e25fd0b4 Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Sun, 17 Feb 2013 12:30:14 +0100
Subject: o Using a bus for the memory input too. o Adding a test case for
 reading data from RAM.

---
 vhdl/mcu_interface.vhd | 35 +++++++++++++++++------------------
 1 file changed, 17 insertions(+), 18 deletions(-)

(limited to 'vhdl/mcu_interface.vhd')

diff --git a/vhdl/mcu_interface.vhd b/vhdl/mcu_interface.vhd
index 86807a7..0aecbf2 100644
--- a/vhdl/mcu_interface.vhd
+++ b/vhdl/mcu_interface.vhd
@@ -13,8 +13,7 @@ entity mcu_interface is
     bit_out             : out std_logic;
     ah                  : out std_logic_vector(7 downto 0);
     al                  : out std_logic_vector(7 downto 0);
-    d_out               : out std_logic_vector(7 downto 0);
-    d_in                : in std_logic_vector(7 downto 0)
+    d                   : inout std_logic_vector(7 downto 0)
   );
 end;
 
@@ -63,14 +62,14 @@ begin
     sck => mcu_in.bit_clk,
     rck => mcu_in.byte_out_clk,
     gneg => mcu_in.d_oe,
-    qa => d_out(0),
-    qb => d_out(1),
-    qc => d_out(2),
-    qd => d_out(3),
-    qe => d_out(4),
-    qf => d_out(5),
-    qg => d_out(6),
-    qh => d_out(7),
+    qa => d(0),
+    qb => d(1),
+    qc => d(2),
+    qd => d(3),
+    qe => d(4),
+    qf => d(5),
+    qg => d(6),
+    qh => d(7),
     SCLRNeg => '1'
   );
 
@@ -81,13 +80,13 @@ begin
     clk => mcu_in.bit_clk,
     clkinh => '0',
     sh => mcu_in.byte_in_clk,
-    da => d_in(0),
-    db => d_in(1),
-    dc => d_in(2),
-    dd => d_in(3),
-    de => d_in(4),
-    df => d_in(5),
-    dg => d_in(6),
-    dh => d_in(7)
+    da => d(0),
+    db => d(1),
+    dc => d(2),
+    dd => d(3),
+    de => d(4),
+    df => d(5),
+    dg => d(6),
+    dh => d(7)
   );
 end;
-- 
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