From 2be1fada10bddbbabe4da448a76f1208aed53c5e Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Sun, 10 Feb 2013 22:00:43 +0100
Subject: wip

---
 vhdl/mcu_interface_tb.vhd | 120 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 120 insertions(+)
 create mode 100644 vhdl/mcu_interface_tb.vhd

(limited to 'vhdl/mcu_interface_tb.vhd')

diff --git a/vhdl/mcu_interface_tb.vhd b/vhdl/mcu_interface_tb.vhd
new file mode 100644
index 0000000..d46df95
--- /dev/null
+++ b/vhdl/mcu_interface_tb.vhd
@@ -0,0 +1,120 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.all;
+
+-- library std;
+-- use std.textio.all;
+
+-- use ieee.std_logic_textio.all;
+library ieee_proposed;
+use ieee_proposed.std_logic_1164_additions.all;
+
+entity mcu_interface_tb is
+end mcu_interface_tb;
+
+-- The MCU has to initialize its output to these values.
+architecture behaviour of mcu_interface_tb is
+  signal bit_in         : std_logic;
+  signal bit_out        : std_logic;
+  signal bit_clk        : std_logic := '0';
+  signal byte_out_clk   : std_logic := '0';
+  signal byte_in_clk    : std_logic := '1'; -- active low
+  signal a_oe           : std_logic := '1';
+  signal d_oe           : std_logic := '1';
+
+  signal ah             : std_logic_vector(7 downto 0);
+  signal al             : std_logic_vector(7 downto 0);
+  signal d_out          : std_logic_vector(7 downto 0);
+  signal d_in           : std_logic_vector(7 downto 0) := "11110000";
+
+  signal byte_in_s      : std_logic_vector(7 downto 0) := "UUUUUUUU";
+
+  constant tClk         : time :=  1 ns;
+begin
+  mcu_interface : entity work.mcu_interface port map(
+        bit_in,
+        bit_out,
+        bit_clk,
+        byte_out_clk,
+        byte_in_clk,
+        a_oe,
+        d_oe,
+        ah,
+        al,
+        d_out,
+        d_in);
+
+  stimulus : process
+    variable byte_in_v  : std_logic_vector(7 downto 0) := "UUUUUUUU";
+
+    -- The MCU will implement these function in software
+    procedure byte_out(byte : in std_logic_vector(7 downto 0)) is
+    begin
+      for i in byte'range loop
+        bit_in  <= byte(i);
+        bit_clk <= '1';
+        wait for tClk;
+
+        bit_clk <= '0';
+        wait for tClk;
+      end loop;
+
+      byte_out_clk <= '1';
+      wait for tClk;
+
+      byte_out_clk <= '0';
+      wait for tClk;
+    end;
+
+    procedure byte_in(byte : out std_logic_vector(7 downto 0)) is
+    begin
+      byte_in_clk <= '0';
+      wait for tClk;
+
+      byte_in_clk <= '1';
+      wait for tClk;
+
+      for i in byte'range loop
+        byte(i) := bit_out;
+        bit_clk <= '1';
+        wait for tClk;
+
+        bit_clk <= '0';
+        wait for tClk;
+      end loop;
+    end;
+
+    procedure write_ram(
+      data      : in std_logic_vector(7 downto 0);
+      address   : in std_logic_vector(15 downto 0)) is
+    begin
+      report "write_ram: " & to_string(data);
+
+      -- TODO: busreq + wait for busack
+      byte_out(data);
+      byte_out(address(7 downto 0));
+      byte_out(address(15 downto 8));
+    end;
+
+  begin
+    write_ram("10100101", "0000000000000001");
+    d_oe <= '0';
+    a_oe <= '0';
+
+    wait for tClk;
+    assert ah = "00000000" report "ah failed";
+    assert al = "00000001" report "al failed";
+    assert d_out = "10100101" report "d_out failed";
+
+    wait for tClk;
+    d_in <= "01011010";
+    wait for 2 * tClk;
+    byte_in(byte_in_v);
+    byte_in_s <= byte_in_v;
+    wait for tClk;
+    assert byte_in_v = "01011010" report "byte_in failed";
+
+    assert false report "end of test" severity note;
+    wait;
+  end process;
+end;
-- 
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