library ieee;
use ieee.std_logic_1164.all;
use work.all;

entity ice_tb is
end ice_tb;

architecture ice_tb_arch of ice_tb is
  signal bit_in      : std_logic;
  signal bit_out     : std_logic;
  signal bit_clk     : std_logic := '0';
  signal byte_clk    : std_logic := '0';
  signal a_oe        : std_logic := '1';
  signal d_oe        : std_logic := '1';

  signal ah          : std_logic_vector(7 downto 0);
  signal al          : std_logic_vector(7 downto 0);
  signal d_out       : std_logic_vector(7 downto 0);

  constant tClk      : time :=  1 ns;
begin
  ice : entity work.ice port map(bit_in, bit_out, bit_clk, byte_clk, a_oe, d_oe, ah, al, d_out);

  stimulus : process
    procedure byte_out(byte  : in std_logic_vector(7 downto 0)) is
    begin
      for i in byte'range loop
        bit_in  <= byte(i);
        bit_clk <= '1';
        wait for tClk;

        bit_clk <= '0';
        wait for tClk;
      end loop;

      byte_clk <= '1';
      wait for tClk;

      byte_clk <= '0';
      wait for tClk;
    end;

    procedure write_ram(
      data      : in std_logic_vector(7 downto 0);
      address   : in std_logic_vector(15 downto 0)) is
    begin
      -- TODO: busreq + wait for busack
      byte_out(data);
      byte_out(address(7 downto 0));
      byte_out(address(15 downto 8));
    end;

  begin
    write_ram("10100101", "0000000000000001");
    d_oe <= '0';
    a_oe <= '0';

    wait for tClk;
    assert ah = "00000000" report "ah failed";
    assert al = "00000001" report "al failed";
    assert d_out = "10100101" report "d_out failed";

    assert false report "end of test" severity note;
    wait;
  end process;
end;