library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu.all;

entity ice_tb is
end;

architecture behavior of ice_tb is
  signal mcu_in         : mcu_in;
  signal bit_out        : std_logic;
  signal oe             : std_logic := disable;
  signal ce             : std_logic := enable;
  signal we             : std_logic := disable;
begin
  ice : entity work.ice port map(
    mcu_in, bit_out, oe, ce, we
  );

  stimulus : process
  begin
    mcu_in <= mcu_in_initial;

    write_ram(mcu_in, we, "10100101", "0000000000000001");
    wait;
  end process;

end;