library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu.all;

entity ice_tb is
end;

architecture behavior of ice_tb is
  signal mcu_in         : mcu_in;
  signal bit_out        : std_logic;
  signal ram_in         : ram_in;
  signal data           : std_logic_vector(7 downto 0);
begin
  ice : entity work.ice port map(
    mcu_in, bit_out, ram_in
  );

  stimulus : process
  begin
    mcu_in <= mcu_in_initial;
    mcu_in.a_oe <= enable;
    ram_in <= ram_in_initial;

    ram_in.ce <= enable;

    write_ram(mcu_in, ram_in, "10100101", "1111000011110000");
    write_ram(mcu_in, ram_in, "01011010", "0000111100001111");

    read_ram(mcu_in, ram_in, bit_out, data, "1111000011110000");

    wait;
  end process;

end;