library ieee;
use ieee.std_logic_1164.all;

library ieee_proposed;
use ieee_proposed.std_logic_1164_additions.all;

-- use work.mcu.all;

package mcu is

  type mcu_in is record
    -- SPI interface
    bit_in              : std_logic;
    bit_clk             : std_logic;

    -- Strobed to latch data from SPI buffer to AH, AL and Dout
    byte_out_clk        : std_logic;
    -- Store to latch data from D bus to Din
    byte_in_clk         : std_logic;
    -- Enable AH and AL, active low
    a_oe                : std_logic; 
    -- Enable Dout, active low
    d_oe                : std_logic; 
  end record;

  procedure byte_out(
    signal mcu_in       : out mcu_in;
    byte                : in std_logic_vector(7 downto 0)
  );

  procedure byte_in(
    signal mcu_in       : out mcu_in;
    signal bit_out      : in std_logic;
    signal byte         : out std_logic_vector(7 downto 0)
  );

  procedure write_ram(
    signal mcu_in       : out mcu_in;
    signal we           : out std_logic;
    data                : in std_logic_vector(7 downto 0);
    address             : in std_logic_vector(15 downto 0)
  );

  constant tClk         : time :=  100 ns;
  constant disable      : std_logic := '1';
  constant enable       : std_logic := '0';

  constant mcu_in_initial : mcu_in := (
    bit_in => '0',
    bit_clk => '1',
    byte_out_clk => '1',
    byte_in_clk => '1',
    a_oe => '1',
    d_oe => '1'
  );

end mcu;

package body mcu is

  procedure byte_out(
    signal mcu_in       : out mcu_in;
    byte                : in std_logic_vector(7 downto 0)) is
  begin
    for i in byte'range loop
      mcu_in.bit_in  <= byte(i);
      mcu_in.bit_clk <= '0';
      wait for tClk;

      mcu_in.bit_clk <= '1';
      wait for tClk;
    end loop;
  end;

  procedure byte_in(
    signal mcu_in       : out mcu_in;
    signal bit_out      : in std_logic;
    signal byte         : out std_logic_vector(7 downto 0)) is
  begin
    mcu_in.byte_in_clk <= '0';
    wait for tClk;

    mcu_in.byte_in_clk <= '1';
    wait for tClk;

    for i in byte'range loop
      byte(i) <= bit_out;
      mcu_in.bit_clk <= '0';
      wait for tClk;

      mcu_in.bit_clk <= '1';
      wait for tClk;
    end loop;
  end;

  procedure write_ram(
    signal mcu_in       : out mcu_in;
    signal we           : out std_logic;
    data                : in std_logic_vector(7 downto 0);
    address             : in std_logic_vector(15 downto 0)) is
  begin
    report "write_ram: " & to_string(data);

    -- TODO: busreq + wait for busack
    byte_out(mcu_in, data);
    byte_out(mcu_in, address(7 downto 0));
    byte_out(mcu_in, address(15 downto 8));

    mcu_in.byte_out_clk <= '0';
    wait for tClk;

    -- Clock the data out on the A and D busses
    mcu_in.byte_out_clk <= '1';
    -- Enable A and D outputs
    mcu_in.a_oe <= enable;
    mcu_in.d_oe <= enable;
    we <= enable;

    wait for tClk;

    we <= disable;
  end;

end mcu;