library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

library fmf;
use fmf.std595;

use work.mcu.all;

entity mcu_interface is
  port (
    mcu_in              : in mcu_in;
    bit_out             : out std_logic;
    ah                  : out std_logic_vector(7 downto 0);
    al                  : out std_logic_vector(7 downto 0);
    d_out               : out std_logic_vector(7 downto 0);
    d_in                : in std_logic_vector(7 downto 0)
  );
end;

architecture behaviour of mcu_interface is
  -- Internal SPI bus signals
  signal ah_out         : std_logic;
  signal al_out         : std_logic;
begin
  ah_buf : entity fmf.std595(vhdl_behavioral) port map(
    ser => mcu_in.bit_in,
    qhser => ah_out,
    sck => mcu_in.bit_clk,
    rck => mcu_in.byte_out_clk,
    gneg => mcu_in.a_oe,
    qa => ah(0),
    qb => ah(1),
    qc => ah(2),
    qd => ah(3),
    qe => ah(4),
    qf => ah(5),
    qg => ah(6),
    qh => ah(7),
    SCLRNeg => '1'
  );

  al_buf : entity fmf.std595(vhdl_behavioral) port map(
    ser => ah_out,
    qhser => al_out,
    sck => mcu_in.bit_clk,
    rck => mcu_in.byte_out_clk,
    gneg => mcu_in.a_oe,
    qa => al(0),
    qb => al(1),
    qc => al(2),
    qd => al(3),
    qe => al(4),
    qf => al(5),
    qg => al(6),
    qh => al(7),
    SCLRNeg => '1'
  );

  d_out_buf : entity fmf.std595(vhdl_behavioral) port map(
    ser => al_out,
    qhser => open,
    sck => mcu_in.bit_clk,
    rck => mcu_in.byte_out_clk,
    gneg => mcu_in.d_oe,
    qa => d_out(0),
    qb => d_out(1),
    qc => d_out(2),
    qd => d_out(3),
    qe => d_out(4),
    qf => d_out(5),
    qg => d_out(6),
    qh => d_out(7),
    SCLRNeg => '1'
  );

  d_in_buf : entity fmf.std165(vhdl_behavioral) port map(
    ser => '0',
    q => bit_out,
    qneg => open,
    clk => mcu_in.bit_clk,
    clkinh => '0',
    sh => mcu_in.byte_in_clk,
    da => d_in(0),
    db => d_in(1),
    dc => d_in(2),
    dd => d_in(3),
    de => d_in(4),
    df => d_in(5),
    dg => d_in(6),
    dh => d_in(7)
  );
end;