library ieee;
use ieee.std_logic_1164.all;

library ieee_proposed;
use ieee_proposed.std_logic_1164_additions.all;

use work.mcu.all;

entity mcu_interface_tb is
end mcu_interface_tb;

-- The MCU has to initialize its output to these values.
architecture behaviour of mcu_interface_tb is
  signal mcu_in         : mcu_in;
--  signal bit_in         : std_logic;
  signal bit_out        : std_logic;
--  signal bit_clk        : std_logic := '0';
--  signal byte_out_clk   : std_logic := '0';
--  signal byte_in_clk    : std_logic := '1'; -- active low
--  signal a_oe           : std_logic := '1';
--  signal d_oe           : std_logic := '1';

  signal ah             : std_logic_vector(7 downto 0);
  signal al             : std_logic_vector(7 downto 0);
  signal d_out          : std_logic_vector(7 downto 0);
  signal d_in           : std_logic_vector(7 downto 0) := "11110000";

  signal byte_in_s      : std_logic_vector(7 downto 0) := "UUUUUUUU";

  constant tClk         : time := tClk;
begin
  mcu_interface : entity work.mcu_interface port map(
        mcu_in,
        bit_out,
        ah,
        al,
        d_out,
        d_in);

  stimulus : process
    variable byte_in_v  : std_logic_vector(7 downto 0) := "UUUUUUUU";

    -- The MCU will implement these function in software
    procedure byte_out(byte : in std_logic_vector(7 downto 0)) is
    begin
      for i in byte'range loop
        mcu_in.bit_in  <= byte(i);
        mcu_in.bit_clk <= '0';
        wait for tClk;

        mcu_in.bit_clk <= '1';
        wait for tClk;
      end loop;
    end;

    procedure byte_in(byte : out std_logic_vector(7 downto 0)) is
    begin
      mcu_in.byte_in_clk <= '0';
      wait for tClk;

      mcu_in.byte_in_clk <= '1';
      wait for tClk;

      for i in byte'range loop
        byte(i) := bit_out;
        mcu_in.bit_clk <= '0';
        wait for tClk;

        mcu_in.bit_clk <= '1';
        wait for tClk;
      end loop;
    end;

    procedure write_ram(
      data      : in std_logic_vector(7 downto 0);
      address   : in std_logic_vector(15 downto 0)) is
    begin
      report "write_ram: " & to_string(data) & "b/0x"  & to_hex_string(data) & "@" & to_hex_string(address);

      -- TODO: busreq + wait for busack
      byte_out(data);
      byte_out(address(7 downto 0));
      byte_out(address(15 downto 8));

      mcu_in.byte_out_clk <= '0';
      wait for tClk;

      mcu_in.byte_out_clk <= '1';
      wait for tClk;
    end;

  begin
--    mcu_in.bit_in <= '0';
--    mcu_in.bit_clk <= '1';
--    mcu_in.byte_out_clk <= '1';
--    mcu_in.byte_in_clk <= '1';
--    mcu_in.a_oe <= '1';
--    mcu_in.d_oe <= '1';
    mcu_in <= mcu_in_initial;

    write_ram("10100101", "0000000000000001");
    mcu_in.d_oe <= '0';
    mcu_in.a_oe <= '0';

    wait for tClk;
    assert ah = "00000000" report "ah failed";
    assert al = "00000001" report "al failed";
    assert d_out = "10100101" report "d_out failed";

    wait for tClk;
    d_in <= "01011010";
    wait for 2 * tClk;
    byte_in(byte_in_v);
    byte_in_s <= byte_in_v;
    wait for tClk;
    assert byte_in_v = "01011010" report "byte_in failed";

    assert false report "end of test" severity note;
    wait;
  end process;
end;