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authorTrygve Laugstøl <trygvis@inamo.no>2016-01-02 21:13:31 +0100
committerTrygve Laugstøl <trygvis@inamo.no>2016-01-02 21:13:31 +0100
commitbaedda497d16c5096971eee83a0c467fe663fe6d (patch)
tree2f8925c68d94aed7d5fc7022462abbb359200b9e /apps/test1
parent9129af503c8211d713c8a160a3b6f3f86b328639 (diff)
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o Moving around a lot of files.
Diffstat (limited to 'apps/test1')
-rw-r--r--apps/test1/CMakeLists.txt24
-rw-r--r--apps/test1/test1.cpp101
2 files changed, 125 insertions, 0 deletions
diff --git a/apps/test1/CMakeLists.txt b/apps/test1/CMakeLists.txt
new file mode 100644
index 0000000..eb090b3
--- /dev/null
+++ b/apps/test1/CMakeLists.txt
@@ -0,0 +1,24 @@
+add_executable(test1.elf test1.cpp
+ ${PLAYGROUND_DIR}/src/init_low.s ${PLAYGROUND_DIR}/src/init_high.cpp ${PLAYGROUND_DIR}/include/init_high.h
+ ${PLAYGROUND_DIR}/include/playground.h
+ ${PLAYGROUND_DIR}/src/debug.cpp ${PLAYGROUND_DIR}/include/debug.h
+ ${PLAYGROUND_DIR}/include/stm32f10x_conf.h
+ # http://www.sparetimelabs.com/tinyprintf/tinyprintf.php
+ ${TINYPRINTF_DIR}/tinyprintf.c ${TINYPRINTF_DIR}/tinyprintf.h
+ ${STM32F10X_STDPERIPH_LIB}/Libraries/CMSIS/CM3/CoreSupport/core_cm3.c
+ ${STM32F10X_STDPERIPH_LIB}/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x/system_stm32f10x.c
+ ${STM32F10X_STDPERIPH_LIB}/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_rcc.c
+ ${STM32F10X_STDPERIPH_LIB}/Libraries/STM32F10x_StdPeriph_Driver/src/stm32f10x_gpio.c
+ )
+
+target_include_directories(test1.elf PUBLIC
+ ${PLAYGROUND_DIR}/include
+ ${TINYPRINTF_DIR}
+ ${STM32F10X_STDPERIPH_LIB}/Libraries/CMSIS/CM3/CoreSupport
+ ${STM32F10X_STDPERIPH_LIB}/Libraries/CMSIS/CM3/DeviceSupport/ST/STM32F10x
+ ${STM32F10X_STDPERIPH_LIB}/Libraries/STM32F10x_StdPeriph_Driver/inc)
+target_compile_definitions(test1.elf PUBLIC ${STM32F10X_STDPERIPH_DEFINES})
+
+target_compile_options(test1.elf PUBLIC "-O0")
+set_target_properties(test1.elf PROPERTIES LINK_FLAGS "-nostartfiles -T${CMAKE_SOURCE_DIR}/cmake/stm32.ld")
+add_extra_commands(test1.elf)
diff --git a/apps/test1/test1.cpp b/apps/test1/test1.cpp
new file mode 100644
index 0000000..a883876
--- /dev/null
+++ b/apps/test1/test1.cpp
@@ -0,0 +1,101 @@
+#include <stdint.h>
+#include <stdint-gcc.h>
+#include <stm32f10x.h>
+#include <stm32f10x_rcc.h>
+#include <stm32f10x_gpio.h>
+#include <stddef.h>
+#include "playground.h"
+
+extern "C"
+__attribute__((naked))
+void HardFault_Handler_C(uint32_t *hardfault_args);
+
+extern "C" void high();
+extern "C" void low();
+
+SCB_Type *__SCB = ((SCB_Type *) SCB_BASE);
+//extern SCB_Type *__SCB;
+
+struct hardfault_data_t {
+ uint32_t r0;
+ uint32_t r1;
+ uint32_t r2;
+ uint32_t r3;
+ uint32_t r12;
+ uint32_t lr;
+ uint32_t pc;
+ uint32_t psr;
+};
+
+volatile struct hardfault_data_t *hardfault_data = (volatile struct hardfault_data_t *) 0x20000800;
+
+void HardFault_Handler_C(uint32_t *hardfault_args) {
+ hardfault_data->r0 = hardfault_args[0];
+ hardfault_data->r1 = hardfault_args[1];
+ hardfault_data->r2 = hardfault_args[2];
+ hardfault_data->r3 = hardfault_args[3];
+ hardfault_data->r12 = hardfault_args[4];
+ hardfault_data->lr = hardfault_args[5];
+ hardfault_data->pc = hardfault_args[6];
+ hardfault_data->psr = hardfault_args[7];
+
+ halt();
+}
+
+void send_command(int command, void *message) {
+ bool active = (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) == CoreDebug_DHCSR_C_DEBUGEN_Msk;
+
+ if (!active) {
+ return;
+ }
+
+ __asm volatile (
+ "mov r0, %[cmd];"
+ "mov r1, %[msg];"
+ "bkpt #0xAB" : : [cmd] "r"(command), [msg] "r"(message) : "r0", "r1", "memory"
+ );
+}
+
+size_t strlen(const char *s) {
+ size_t size = 0;
+ while (*s++ != '\0') size++;
+ return size;
+}
+
+int run = 1;
+
+/*
+ * When we get there the stack pointer is set
+ */
+int main() {
+ SystemInit();
+// SystemCoreClockUpdate();
+
+ SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTPENDED_Msk | SCB_SHCSR_BUSFAULTENA_Msk;
+
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
+
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
+
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOA,
+ ENABLE);
+
+ GPIO_InitTypeDef init;
+ GPIO_StructInit(&init);
+ init.GPIO_Mode = GPIO_Mode_Out_PP;
+ GPIO_Init(GPIOB, &init);
+
+ while (run) {
+// GPIO_SetBits(GPIOA, GPIO_Pin_All);
+ GPIO_SetBits(GPIOB, GPIO_Pin_All);
+// GPIO_SetBits(GPIOC, GPIO_Pin_All);
+
+// GPIO_ResetBits(GPIOA, GPIO_Pin_All);
+ GPIO_ResetBits(GPIOB, GPIO_Pin_All);
+// GPIO_ResetBits(GPIOC, GPIO_Pin_All);
+ }
+
+ return 0;
+}