diff options
| -rw-r--r-- | gdb-start | 31 | ||||
| -rw-r--r-- | test1.cpp | 109 |
2 files changed, 88 insertions, 52 deletions
@@ -1,28 +1,19 @@ target remote tcp:localhost:3333 -file build/test1.elf -load build/test1.elf - -# Write 0x5000 (20k) with the pattern 0x5a -monitor stm32f1x.cpu mwb 0x20000000 0x5a 0x5000 - -#monitor stm32f1x.cpu mww 0x40010c00 0x55555555 1 -#monitor stm32f1x.cpu mww 0x40010c04 0x55555555 1 -# BSRR -#monitor stm32f1x.cpu mww 0x40010c10 0xffff0000 1 -#monitor stm32f1x.cpu mww 0x40010c10 0x0000ffff 1 - -# ODR -# monitor stm32f1x.cpu mww 0x40010c0c 0x0000ffff 1 define flash_test1 -file build/test1.elf -#load build/test1.elf +monitor arm semihosting enable monitor reset halt -monitor flash probe 0 -monitor stm32f1x mass_erase 0 + monitor stm32f1x.cpu mwb 0x20000000 0x5a 20480 -monitor flash write_bank 0 test1.elf.bin 0 -monitor arm semihosting enable + +set confirm off +file build/test1.elf +load build/test1.elf +set confirm on + +#monitor flash probe 0 +#monitor stm32f1x mass_erase 0 +#monitor flash write_bank 0 test1.elf.bin 0 # delete breakpoint # hbreak main end @@ -12,7 +12,7 @@ int main(void); extern "C" __attribute__((naked)) -void HardFault_Handler_C(uint32_t * hardfault_args); +void HardFault_Handler_C(uint32_t *hardfault_args); extern "C" void high(); extern "C" void low(); @@ -31,9 +31,9 @@ struct hardfault_data_t { uint32_t psr; }; -volatile struct hardfault_data_t *hardfault_data = (volatile struct hardfault_data_t *)0x20000800; +volatile struct hardfault_data_t *hardfault_data = (volatile struct hardfault_data_t *) 0x20000800; -void HardFault_Handler_C(uint32_t * hardfault_args) { +void HardFault_Handler_C(uint32_t *hardfault_args) { hardfault_data->r0 = hardfault_args[0]; hardfault_data->r1 = hardfault_args[1]; hardfault_data->r2 = hardfault_args[2]; @@ -47,51 +47,96 @@ void HardFault_Handler_C(uint32_t * hardfault_args) { } while (1); } -__attribute__((naked)) -void send_command(int command, void* message) { - __asm volatile ( - "mov r0, %[cmd] \n\t" - "mov r1, %[msg] \n\t" - "bkpt #0xAB" : : [cmd] "r" (command), [msg] "r" (message) : "r0", "r1", "memory" - ); +void send_command(int command, void *message) { + __asm volatile ( + "mov r0, %[cmd];" + "mov r1, %[msg];" + "bkpt #0xAB" : : [cmd] "r"(command), [msg] "r"(message) : "r0", "r1", "memory" + ); } int main() { uint32_t message[] = { 2, - (uint32_t)"Hello World!\r\n", - 14 + (uint32_t) "Hello World! again\r\n", + 20 }; send_command(0x05, &message); SystemInit(); + SystemCoreClockUpdate(); +// RCC->APB2ENR = RCC_APB2ENR_IOPCEN; SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTPENDED_Msk | SCB_SHCSR_BUSFAULTENA_Msk; - RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); -// GPIO_InitTypeDef init; -// GPIO_StructInit(&init); -// init.GPIO_Mode = GPIO_Mode_Out_PP; -// init.GPIO_Pin = + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); - do { - volatile uint32_t *port_b = (uint32_t *) (0x40010c00); - volatile uint32_t *port_b_crl = (uint32_t *) (port_b + 0x00); - volatile uint32_t *port_b_crh = (uint32_t *) (port_b + 0x04); - volatile uint32_t *port_b_idr = (uint32_t *) (port_b + 0x08); - volatile uint32_t *port_b_odr = (uint32_t *) (port_b + 0x0c); - volatile uint32_t *port_b_bsrr = (uint32_t *) (port_b + 0x10); - volatile uint32_t *port_b_brr = (uint32_t *) (port_b + 0x14); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOA, + ENABLE); - // mode=output, max speed 10MHz - *port_b_crl = 0x11111111; - *port_b_crh = 0x11111111; + if (1) { + GPIO_InitTypeDef init; + GPIO_StructInit(&init); + init.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOB, &init); - *port_b_bsrr = 0xffff0000; + while (1) { + GPIO_SetBits(GPIOA, GPIO_Pin_All); + GPIO_SetBits(GPIOB, GPIO_Pin_All); + GPIO_SetBits(GPIOC, GPIO_Pin_All); - *port_b_bsrr = 0x0000ffff; - } while (1); +// send_command(0x05, &message); + + GPIO_ResetBits(GPIOA, GPIO_Pin_All); + GPIO_ResetBits(GPIOB, GPIO_Pin_All); + GPIO_ResetBits(GPIOC, GPIO_Pin_All); + +// send_command(0x05, &message); + } + } + + if (0) { + GPIOA->CRL &= ~(GPIO_CRL_MODE0 | GPIO_CRL_CNF0); + GPIOA->CRL |= GPIO_CRL_MODE0; + + GPIOB->CRL &= ~(GPIO_CRL_MODE5 | GPIO_CRL_CNF5); + GPIOB->CRL |= GPIO_CRL_MODE5; + + while (1) { + GPIOB->BSRR = -1; + GPIOB->BSRR = -1; + + send_command(0x05, &message); + + GPIOA->BRR = -1; + GPIOA->BRR = -1; + + send_command(0x05, &message); + } + } + + if (0) { + do { + volatile uint32_t *port_b = (uint32_t *) (0x40010c00); + volatile uint32_t *port_b_crl = (uint32_t *) (port_b + 0x00); + volatile uint32_t *port_b_crh = (uint32_t *) (port_b + 0x04); +// volatile uint32_t *port_b_idr = (uint32_t *) (port_b + 0x08); +// volatile uint32_t *port_b_odr = (uint32_t *) (port_b + 0x0c); + volatile uint32_t *port_b_bsrr = (uint32_t *) (port_b + 0x10); +// volatile uint32_t *port_b_brr = (uint32_t *) (port_b + 0x14); + + // mode=output, max speed 10MHz + *port_b_crl = 0x11111111; + *port_b_crh = 0x11111111; + + *port_b_bsrr = 0xffff0000; + + *port_b_bsrr = 0x0000ffff; + } while (1); + } return 0; } |