diff options
Diffstat (limited to 'thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL')
10 files changed, 729 insertions, 0 deletions
diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl new file mode 100644 index 0000000..77a6526 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10x_hd.lsl @@ -0,0 +1,165 @@ +//////////////////////////////////////////////////////////////////////////// +// +// File : stm32f103_cmsis.lsl +// +// Version : @(#)stm32f103_cmsis.lsl 1.2 09/06/04 +// +// Description : LSL file for the STMicroelectronics STM32F103, CMSIS version +// +// Copyright 2009 Altium BV +// +// NOTE: +// This file is derived from cm3.lsl and stm32f103.lsl. +// It is assumed that the user works with the ARMv7M architecture. +// Other architectures will not work with this lsl file. +// +//////////////////////////////////////////////////////////////////////////// + +// +// We do not want the vectors as defined in arm_arch.lsl +// +#define __NO_DEFAULT_AUTO_VECTORS 1 +#define __NR_OF_VECTORS 76 + + +#ifndef __STACK +# define __STACK 8k +#endif +#ifndef __HEAP +# define __HEAP 2k +#endif +#ifndef __VECTOR_TABLE_ROM_ADDR +# define __VECTOR_TABLE_ROM_ADDR 0x08000000 +#endif +#ifndef __XVWBUF +#define __XVWBUF 256 /* buffer used by CrossView */ +#endif + +#include <arm_arch.lsl> + +//////////////////////////////////////////////////////////////////////////// +// +// In the STM32F10x, 3 different boot modes can be selected +// - User Flash memory is selected as boot space +// - SystemMemory is selected as boot space +// - Embedded SRAM is selected as boot space +// +// This aliases the physical memory associated with each boot mode to Block +// 000 (0x00000000 boot memory). Even when aliased in the boot memory space, +// the related memory (Flash memory or SRAM) is still accessible at its +// original memory space. +// +// If no memory is defined yet use the following memory settings +// +#ifndef __MEMORY + +memory stm32f103flash +{ + mau = 8; + type = rom; + size = 512k; + map ( size = 512k, dest_offset=0x08000000, dest=bus:ARM:local_bus); +} + +memory stm32f103ram +{ + mau = 8; + type = ram; + size = 64k; + map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus); +} + +#endif /* __MEMORY */ + + +// +// Custom vector table defines interrupts according to CMSIS standard +// +# if defined(__CPU_ARMV7M__) +section_setup ::linear +{ + // vector table with handler addresses + vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR, + template = ".text.handler_address", + template_symbol = "_lc_vector_handler", + vector_prefix = "_vector_", + fill = loop, + no_inline + ) + { + vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work + vector ( id = 1, fill = "_START" ); + vector ( id = 2, optional, fill = "NMI_Handler" ); + vector ( id = 3, optional, fill = "HardFault_Handler" ); + vector ( id = 4, optional, fill = "MemManage_Handler" ); + vector ( id = 5, optional, fill = "BusFault_Handler" ); + vector ( id = 6, optional, fill = "UsageFault_Handler" ); + vector ( id = 11, optional, fill = "SVC_Handler" ); + vector ( id = 12, optional, fill = "DebugMon_Handler" ); + vector ( id = 14, optional, fill = "PendSV_Handler" ); + vector ( id = 15, optional, fill = "SysTick_Handler" ); + + // External Interrupts : + vector ( id = 16, optional, fill = "WWDG_IRQHandler" ); // Window Watchdog + vector ( id = 17, optional, fill = "PVD_IRQHandler" ); // PVD through EXTI Line detect + vector ( id = 18, optional, fill = "TAMPER_IRQHandler" ); // Tamper + vector ( id = 19, optional, fill = "RTC_IRQHandler" ); // RTC + vector ( id = 20, optional, fill = "FLASH_IRQHandler" ); // Flash + vector ( id = 21, optional, fill = "RCC_IRQHandler" ); // RCC + vector ( id = 22, optional, fill = "EXTI0_IRQHandler" ); // EXTI Line 0 + vector ( id = 23, optional, fill = "EXTI1_IRQHandler" ); // EXTI Line 1 + vector ( id = 24, optional, fill = "EXTI2_IRQHandler" ); // EXTI Line 2 + vector ( id = 25, optional, fill = "EXTI3_IRQHandler" ); // EXTI Line 3 + vector ( id = 26, optional, fill = "EXTI4_IRQHandler" ); // EXTI Line 4 + vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" ); // DMA Channel 1 + vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" ); // DMA Channel 2 + vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" ); // DMA Channel 3 + vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" ); // DMA Channel 4 + vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" ); // DMA Channel 5 + vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" ); // DMA Channel 6 + vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" ); // DMA Channel 7 + vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" ); // ADC1 and ADC2 + vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" ); // USB High Priority or CAN1 TX + vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" ); // USB LowPriority or CAN1 RX0 + vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" ); // CAN1 RX1 + vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" ); // CAN1 SCE + vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" ); // EXTI Line 9..5 + vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" ); // TIM1 Break + vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" ); // TIM1 Update + vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" ); // TIM1 Trigger and Commutation + vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" ); // TIM1 Capture Compare + vector ( id = 44, optional, fill = "TIM2_IRQHandler" ); // TIM2 + vector ( id = 45, optional, fill = "TIM3_IRQHandler" ); // TIM3 + vector ( id = 46, optional, fill = "TIM4_IRQHandler" ); // TIM4 + vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" ); // I2C1 Event + vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" ); // I2C1 Error + vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" ); // I2C2 Event + vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" ); // I2C2 Error + vector ( id = 51, optional, fill = "SPI1_IRQHandler" ); // SPI1 + vector ( id = 52, optional, fill = "SPI2_IRQHandler" ); // SPI2 + vector ( id = 53, optional, fill = "USART1_IRQHandler" ); // USART1 + vector ( id = 54, optional, fill = "USART2_IRQHandler" ); // USART2 + vector ( id = 55, optional, fill = "USART3_IRQHandler" ); // USART3 + vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" ); // EXTI Line 15..10 + vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" ); // RTC Alarm through EXTI Line + vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" ); // USB Wakeup from suspend + vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" ); // TIM8 Break + vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" ); // TIM8 Update + vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" ); // TIM8 Trigger and Commutation + vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" ); // TIM8 Capture Compare + vector ( id = 63, optional, fill = "ADC3_IRQHandler" ); // ADC3 + vector ( id = 64, optional, fill = "FSMC_IRQHandler" ); // FSMC + vector ( id = 65, optional, fill = "SDIO_IRQHandler" ); // SDIO + vector ( id = 66, optional, fill = "TIM5_IRQHandler" ); // TIM5 + vector ( id = 67, optional, fill = "SPI3_IRQHandler" ); // SPI3 + vector ( id = 68, optional, fill = "UART4_IRQHandler" ); // UART4 + vector ( id = 69, optional, fill = "UART5_IRQHandler" ); // UART5 + vector ( id = 70, optional, fill = "TIM6_IRQHandler" ); // TIM6 + vector ( id = 71, optional, fill = "TIM7_IRQHandler" ); // TIM7 + vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" ); // DMA2 Channel1 + vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" ); // DMA2 Channel2 + vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" ); // DMA2 Channel3 + vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" ); // DMA2 Channel4 and DMA2 Channel5 + } +} +# endif diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10xnor.lsl b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10xnor.lsl new file mode 100644 index 0000000..5b781d8 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/STM32F10xnor.lsl @@ -0,0 +1,165 @@ +//////////////////////////////////////////////////////////////////////////// +// +// File : stm32f103_cmsis.lsl +// +// Version : @(#)stm32f103_cmsis.lsl 1.2 09/06/04 +// +// Description : LSL file for the STMicroelectronics STM32F103, CMSIS version +// +// Copyright 2009 Altium BV +// +// NOTE: +// This file is derived from cm3.lsl and stm32f103.lsl. +// It is assumed that the user works with the ARMv7M architecture. +// Other architectures will not work with this lsl file. +// +//////////////////////////////////////////////////////////////////////////// + +// +// We do not want the vectors as defined in arm_arch.lsl +// +#define __NO_DEFAULT_AUTO_VECTORS 1 +#define __NR_OF_VECTORS 76 + + +#ifndef __STACK +# define __STACK 8k +#endif +#ifndef __HEAP +# define __HEAP 2k +#endif +#ifndef __VECTOR_TABLE_ROM_ADDR +# define __VECTOR_TABLE_ROM_ADDR 0x64000000 +#endif +#ifndef __XVWBUF +#define __XVWBUF 256 /* buffer used by CrossView */ +#endif + +#include <arm_arch.lsl> + +//////////////////////////////////////////////////////////////////////////// +// +// In the STM32F10x, 3 different boot modes can be selected +// - User Flash memory is selected as boot space +// - SystemMemory is selected as boot space +// - Embedded SRAM is selected as boot space +// +// This aliases the physical memory associated with each boot mode to Block +// 000 (0x00000000 boot memory). Even when aliased in the boot memory space, +// the related memory (Flash memory or SRAM) is still accessible at its +// original memory space. +// +// If no memory is defined yet use the following memory settings +// +#ifndef __MEMORY + +memory stm32f103flash +{ + mau = 8; + type = rom; + size = 8192k; + map ( size = 512k, dest_offset= 0x64000000, dest=bus:ARM:local_bus); +} + +memory stm32f103ram +{ + mau = 8; + type = ram; + size = 64k; + map ( size = 64k, dest_offset=0x20000000, dest=bus:ARM:local_bus); +} + +#endif /* __MEMORY */ + + +// +// Custom vector table defines interrupts according to CMSIS standard +// +# if defined(__CPU_ARMV7M__) +section_setup ::linear +{ + // vector table with handler addresses + vector_table "vector_table" ( vector_size = 4, size = __NR_OF_VECTORS, run_addr = __VECTOR_TABLE_ROM_ADDR, + template = ".text.handler_address", + template_symbol = "_lc_vector_handler", + vector_prefix = "_vector_", + fill = loop, + no_inline + ) + { + vector ( id = 0, fill = "_START" ); // FIXME: "_lc_ub_stack" does not work + vector ( id = 1, fill = "_START" ); + vector ( id = 2, optional, fill = "NMI_Handler" ); + vector ( id = 3, optional, fill = "HardFault_Handler" ); + vector ( id = 4, optional, fill = "MemManage_Handler" ); + vector ( id = 5, optional, fill = "BusFault_Handler" ); + vector ( id = 6, optional, fill = "UsageFault_Handler" ); + vector ( id = 11, optional, fill = "SVC_Handler" ); + vector ( id = 12, optional, fill = "DebugMon_Handler" ); + vector ( id = 14, optional, fill = "PendSV_Handler" ); + vector ( id = 15, optional, fill = "SysTick_Handler" ); + + // External Interrupts : + vector ( id = 16, optional, fill = "WWDG_IRQHandler" ); // Window Watchdog + vector ( id = 17, optional, fill = "PVD_IRQHandler" ); // PVD through EXTI Line detect + vector ( id = 18, optional, fill = "TAMPER_IRQHandler" ); // Tamper + vector ( id = 19, optional, fill = "RTC_IRQHandler" ); // RTC + vector ( id = 20, optional, fill = "FLASH_IRQHandler" ); // Flash + vector ( id = 21, optional, fill = "RCC_IRQHandler" ); // RCC + vector ( id = 22, optional, fill = "EXTI0_IRQHandler" ); // EXTI Line 0 + vector ( id = 23, optional, fill = "EXTI1_IRQHandler" ); // EXTI Line 1 + vector ( id = 24, optional, fill = "EXTI2_IRQHandler" ); // EXTI Line 2 + vector ( id = 25, optional, fill = "EXTI3_IRQHandler" ); // EXTI Line 3 + vector ( id = 26, optional, fill = "EXTI4_IRQHandler" ); // EXTI Line 4 + vector ( id = 27, optional, fill = "DMA1_Channel1_IRQHandler" ); // DMA Channel 1 + vector ( id = 28, optional, fill = "DMA1_Channel2_IRQHandler" ); // DMA Channel 2 + vector ( id = 29, optional, fill = "DMA1_Channel3_IRQHandler" ); // DMA Channel 3 + vector ( id = 30, optional, fill = "DMA1_Channel4_IRQHandler" ); // DMA Channel 4 + vector ( id = 31, optional, fill = "DMA1_Channel5_IRQHandler" ); // DMA Channel 5 + vector ( id = 32, optional, fill = "DMA1_Channel6_IRQHandler" ); // DMA Channel 6 + vector ( id = 33, optional, fill = "DMA1_Channel7_IRQHandler" ); // DMA Channel 7 + vector ( id = 34, optional, fill = "ADC1_2_IRQHandler" ); // ADC1 and ADC2 + vector ( id = 35, optional, fill = "USB_HP_CAN1_TX_IRQHandler" ); // USB High Priority or CAN1 TX + vector ( id = 36, optional, fill = "USB_LP_CAN1_RX0_IRQHandler" ); // USB LowPriority or CAN1 RX0 + vector ( id = 37, optional, fill = "CAN1_RX1_IRQHandler" ); // CAN1 RX1 + vector ( id = 38, optional, fill = "CAN1_SCE_IRQHandler" ); // CAN1 SCE + vector ( id = 39, optional, fill = "EXTI9_5_IRQHandler" ); // EXTI Line 9..5 + vector ( id = 40, optional, fill = "TIM1_BRK_IRQHandler" ); // TIM1 Break + vector ( id = 41, optional, fill = "TIM1_UP_IRQHandler" ); // TIM1 Update + vector ( id = 42, optional, fill = "TIM1_TRG_COM_IRQHandler" ); // TIM1 Trigger and Commutation + vector ( id = 43, optional, fill = "TIM1_CC_IRQHandler" ); // TIM1 Capture Compare + vector ( id = 44, optional, fill = "TIM2_IRQHandler" ); // TIM2 + vector ( id = 45, optional, fill = "TIM3_IRQHandler" ); // TIM3 + vector ( id = 46, optional, fill = "TIM4_IRQHandler" ); // TIM4 + vector ( id = 47, optional, fill = "I2C1_EV_IRQHandler" ); // I2C1 Event + vector ( id = 48, optional, fill = "I2C1_ER_IRQHandler" ); // I2C1 Error + vector ( id = 49, optional, fill = "I2C2_EV_IRQHandler" ); // I2C2 Event + vector ( id = 50, optional, fill = "I2C2_ER_IRQHandler" ); // I2C2 Error + vector ( id = 51, optional, fill = "SPI1_IRQHandler" ); // SPI1 + vector ( id = 52, optional, fill = "SPI2_IRQHandler" ); // SPI2 + vector ( id = 53, optional, fill = "USART1_IRQHandler" ); // USART1 + vector ( id = 54, optional, fill = "USART2_IRQHandler" ); // USART2 + vector ( id = 55, optional, fill = "USART3_IRQHandler" ); // USART3 + vector ( id = 56, optional, fill = "EXTI15_10_IRQHandler" ); // EXTI Line 15..10 + vector ( id = 57, optional, fill = "RTCAlarm_IRQHandler" ); // RTC Alarm through EXTI Line + vector ( id = 58, optional, fill = "USBWakeUp_IRQHandler" ); // USB Wakeup from suspend + vector ( id = 59, optional, fill = "TIM8_BRK_IRQHandler" ); // TIM8 Break + vector ( id = 60, optional, fill = "TIM8_UP_IRQHandler" ); // TIM8 Update + vector ( id = 61, optional, fill = "TIM8_TRG_COM_IRQHandler" ); // TIM8 Trigger and Commutation + vector ( id = 62, optional, fill = "TIM8_CC_IRQHandler" ); // TIM8 Capture Compare + vector ( id = 63, optional, fill = "ADC3_IRQHandler" ); // ADC3 + vector ( id = 64, optional, fill = "FSMC_IRQHandler" ); // FSMC + vector ( id = 65, optional, fill = "SDIO_IRQHandler" ); // SDIO + vector ( id = 66, optional, fill = "TIM5_IRQHandler" ); // TIM5 + vector ( id = 67, optional, fill = "SPI3_IRQHandler" ); // SPI3 + vector ( id = 68, optional, fill = "UART4_IRQHandler" ); // UART4 + vector ( id = 69, optional, fill = "UART5_IRQHandler" ); // UART5 + vector ( id = 70, optional, fill = "TIM6_IRQHandler" ); // TIM6 + vector ( id = 71, optional, fill = "TIM7_IRQHandler" ); // TIM7 + vector ( id = 72, optional, fill = "DMA2_Channel1_IRQHandler" ); // DMA2 Channel1 + vector ( id = 73, optional, fill = "DMA2_Channel2_IRQHandler" ); // DMA2 Channel2 + vector ( id = 74, optional, fill = "DMA2_Channel3_IRQHandler" ); // DMA2 Channel3 + vector ( id = 75, optional, fill = "DMA2_Channel4_5_IRQHandler" ); // DMA2 Channel4 and DMA2 Channel5 + } +} +# endif diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/StartupScript.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/StartupScript.scr new file mode 100644 index 0000000..e3dbe23 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/StartupScript.scr @@ -0,0 +1,9 @@ +// Hitex/Lue/11.02.2008 +// Executable Script file for HiTOP Debugger +// Reset application + +// Reset +RESET TARGET + + + diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr new file mode 100644 index 0000000..4dbe250 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/flash_nor.scr @@ -0,0 +1,102 @@ +// Hitex/We/04.02.2008 +// +// StartupScript Script file for HiTOP Debugger +// Target Hitex evaluation board with STM32Fxxx +// Flash application + +//######################################################################################### +// Enable APB2 GPIOA .. GPIOG + AFIO Peripheral Clock +// +// Register RCC_APB2ENR Adr: 0x40021000 + Offs. 0x18 value 0x1FD +//######################################################################################### +OUTPUT DWORD TO 0x40021014 = 0x00000114 +OUTPUT DWORD TO 0x40021018 = 0x000001FD + + +//######################################################################################### +// NOR Datalines GPIOD, GPIOE +// +// Set Bits 0,1,8,9,10,14,15 of Port D to PushPull, 50Mhz Speed +// Register GPIOD_CRL Adr: 0x40011400 + Offs. 0x00 value 0x444444BB +// Register GPIOD_CRH Adr: 0x40011400 + Offs. 0x04 value 0xBB444BBB +// +// Set Bits 7,8,9,10,11,12,13,14,15 of Port E to PushPull, 50Mhz Speed +// Register GPIOD_CRL Adr: 0x40011800 + Offs. 0x00 value 0xB4444444 +// Register GPIOD_CRH Adr: 0x40011800 + Offs. 0x04 value 0xBBBBBBBB +// +//######################################################################################### +// Port D +OUTPUT DWORD TO 0x40011400 = 0x44BB44BB +OUTPUT DWORD TO 0x40011404 = 0xBBBBBBBB +// Port E +OUTPUT DWORD TO 0x40011800 = 0xBBBBBB44 +OUTPUT DWORD TO 0x40011804 = 0xBBBBBBBB + +//######################################################################################### +// NOR Addresslines GPIOF, GPIOG +// +// Set Bits 0,1,2,3,4,5,12,13,14,15 of Port F to PushPull, 50Mhz Speed +// Register GPIOF_CRL Adr: 0x40011C00 + Offs. 0x00 value 0x444BBBBB +// Register GPIOF_CRH Adr: 0x40011C00 + Offs. 0x04 value 0xBBBB4444 +// +// Set Bits 0,1,2,3,4,5,13,14 of Port G to PushPull, 50Mhz Speed +// Register GPIOG_CRL Adr: 0x40012000 + Offs. 0x00 value 0x44BBBBBB +// Register GPIOG_CRH Adr: 0x40012000 + Offs. 0x04 value 0x4BB44444 +// +// Set Bits 11,12,13 of Port D to PushPull, 50Mhz Speed +// Register GPIOD_CRH Adr: 0x40011400 + Offs. 0x04 value 0xBBBBBBBB +// +// Set Bits 2,3,4,5,6 of Port E to PushPull, 50Mhz Speed +// Register GPIOD_CRL Adr: 0x40011800 + Offs. 0x00 value 0xB4444444 +//######################################################################################### +// Port F +OUTPUT DWORD TO 0x40011C00 = 0x44BBBBBB +OUTPUT DWORD TO 0x40011C04 = 0xBBBB4444 +// Port G +OUTPUT DWORD TO 0x40012000 = 0x44BBBBBB +OUTPUT DWORD TO 0x40012004 = 0x4BB444B4 +// Port D +//OUTPUT DWORD TO 0x40011404 = 0xBBBBBBBB +// Port E +//OUTPUT DWORD TO 0x40011800 = 0xBBBBBBB4 + +//######################################################################################### +// NOE and NWE Configuration GPIOD +// +// Set Bits 4,5 of Port D to PushPull, 50Mhz Speed +// Register GPIOD_CRL Adr: 0x40011400 + Offs. 0x00 value 0x44BB44BB +// +//######################################################################################### +// Port D +//OUTPUT DWORD TO 0x40011400 = 0x44BB44BB + +//######################################################################################### +// NE2 Configuration GPIOG +// +// Set Bits 9 Port G to PushPull, 50Mhz Speed +// Register GPIOD_CRH Adr: 0x40012000 + Offs. 0x04 value 0x4BB444B4 +// +//######################################################################################### +// Port G +//OUTPUT DWORD TO 0x40012004 = 0x4BB444B4 + +//######################################################################################### +// FSMC Configuration +// +// Bank1 is used +// if another Bank is required, then adjust the Register Addresses +// +// Register FSMC_BCR value 0x00001059 +// Register FSMC_BTR value 0x00010112 +// Register FSMC_BWTR value 0x0FFFFFFF +//######################################################################################### + +OUTPUT DWORD TO 0xA0000000 = 0x000030DB + + +OUTPUT DWORD TO 0xA0000008 = 0x00001059 + +OUTPUT DWORD TO 0xA000000C= 0x30010112 + +OUTPUT DWORD TO 0xA0000104 = 0x0FFFFFFF + diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/link.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/link.lnk new file mode 100644 index 0000000..b4d7818 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/link.lnk @@ -0,0 +1,4 @@ +-d"./settings/STM32F10x_hd.lsl" +--optimize=0 +--map-file-format=2 +$(LinkObjects) diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk new file mode 100644 index 0000000..c14afff --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/linknor.lnk @@ -0,0 +1,4 @@ +-d"./settings/STM32F10xnor.lsl" +--optimize=0 +--map-file-format=2 +$(LinkObjects) diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr new file mode 100644 index 0000000..d90eb15 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_appl.scr @@ -0,0 +1,8 @@ +// Hitex/Lue/11.02.2008 +// Executable Script file for HiTOP Debugger +// Reset application + +// Reset +RESET TARGET + + diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_go_main.scr b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_go_main.scr new file mode 100644 index 0000000..3e9c066 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/Settings/reset_go_main.scr @@ -0,0 +1,12 @@ +// Hitex/Lue/11.02.2008 +// Executable Script file for HiTOP Debugger +// Reset application & Go main + +// Reset +RESET TARGET + + +// execute program till main +Go UNTIL main +wait + diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/cstart_thumb2.asm b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/cstart_thumb2.asm new file mode 100644 index 0000000..12dc0d0 --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/cstart_thumb2.asm @@ -0,0 +1,148 @@ + + +;; NOTE: To allow the use of this file for both ARMv6M and ARMv7M, +;; we will only use 16-bit Thumb intructions. + + .extern _lc_ub_stack ; usr/sys mode stack pointer + .extern _lc_ue_stack ; symbol required by debugger + .extern _lc_ub_table ; ROM to RAM copy table + .extern main + .extern _Exit + .extern exit + .weak exit + .global __get_argcv + .weak __get_argcv + .extern __argcvbuf + .weak __argcvbuf + .extern __init_hardware + .extern __init_vector_table + .extern SystemInit + + .if @defined('__PROF_ENABLE__') + .extern __prof_init + .endif + .if @defined('__POSIX__') + .extern posix_main + .extern _posix_boot_stack_top + .endif + + .global _START + + .section .text.cstart + + .thumb +_START: + ;; anticipate possible ROM/RAM remapping + ;; by loading the 'real' program address + ldr r1,=_Next + bx r1 +_Next: + ;; initialize the stack pointer + ldr r1,=_lc_ub_stack ; TODO: make this part of the vector table + mov sp,r1 + + ;; call a user function which initializes hardware + ;; such as ROM/RAM re-mapping or MMU configuration + bl __init_hardware + + ;ldr r0, =SystemInit + ;bx r0 + bl SystemInit + + ;; copy initialized sections from ROM to RAM + ;; and clear uninitialized data sections in RAM + + ldr r3,=_lc_ub_table + movs r0,#0 +cploop: + ldr r4,[r3,#0] ; load type + ldr r5,[r3,#4] ; dst address + ldr r6,[r3,#8] ; src address + ldr r7,[r3,#12] ; size + + cmp r4,#1 + beq copy + cmp r4,#2 + beq clear + b done + +copy: + subs r7,r7,#1 + ldrb r1,[r6,r7] + strb r1,[r5,r7] + bne copy + + adds r3,r3,#16 + b cploop + +clear: + subs r7,r7,#1 + strb r0,[r5,r7] + bne clear + + adds r3,r3,#16 + b cploop + +done: + ;; initialize or copy the vector table + bl __init_vector_table + + .if @defined('__POSIX__') + + ;; posix stack buffer for system upbringing + ldr r0,=_posix_boot_stack_top + ldr r0, [r0] + mov sp,r0 + + .else + + ;; load r10 with end of USR/SYS stack, which is + ;; needed in case stack overflow checking is on + ;; NOTE: use 16-bit instructions only, for ARMv6M + ldr r0,=_lc_ue_stack + mov r10,r0 + + .endif + + .if @defined('__PROF_ENABLE__') + bl __prof_init + .endif + + .if @defined('__POSIX__') + ;; call posix_main with no arguments + bl posix_main + .else + ;; retrieve argc and argv (default argv[0]==NULL & argc==0) + bl __get_argcv + ldr r1,=__argcvbuf + ;; call main + bl main + .endif + + ;; call exit using the return value from main() + ;; Note. Calling exit will also run all functions + ;; that were supplied through atexit(). + bl exit + +__get_argcv: ; weak definition + movs r0,#0 + bx lr + + .ltorg + .endsec + + .calls '_START','__init_hardware' + .calls '_START','__init_vector_table' + .if @defined('__PROF_ENABLE__') + .calls '_START','__prof_init' + .endif + .if @defined('__POSIX__') + .calls '_START','posix_main' + .else + .calls '_START','__get_argcv' + .calls '_START','main' + .endif + .calls '_START','exit' + .calls '_START','',0 + + .end diff --git a/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt new file mode 100644 index 0000000..7e4c10b --- /dev/null +++ b/thirdparty/STM32F10x_StdPeriph_Lib_V3.5.0/Project/STM32F10x_StdPeriph_Template/HiTOP/STM3210E-EVAL/readme.txt @@ -0,0 +1,112 @@ +/** + @page HiTOP5_STM3210E HiTOP Project Template for STM32F10x High-density devices + + @verbatim + ******************** (C) COPYRIGHT 2011 STMicroelectronics ******************* + * @file readme.txt + * @author MCD Application Team + * @version V3.5.0 + * @date 08-April-2011 + * @brief This sub directory contains all the user modifiable files needed + * to create a new project linked with the STM32F10x Standard Peripherals + * Library and working with HiTOP software toolchain (version 5.40 and later). + ****************************************************************************** + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. + * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, + * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE + * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING + * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + ****************************************************************************** + @endverbatim + +@par Directory contents + + - Project.htp: A pre-configured project file with the provided library + structure that produces an executable image with HiTOP + + - cstart_thumb2.asm: This file initializes the stack pointer and copy initialized + sections from ROM to RAM. + + - Objects: This mandatory directory contains the executable images. + + - Settings: This directory contains the linker and script files. + - arm_arch.lsl: This file is used to place program code (readonly) + in internal FLASH and data (readwrite, Stack and Heap) + in internal SRAM. + + - flash_nor.scr: This file is a HiTOP script allowing the FSMC configuration. + It should be executed before programming the NOR flash of the + STM32 High-density devices. + + - link.lnk: This file is the HiTOP linker it invokes the STM32F10x_hd.lsl. + + - linkextsram.lnk: This file is the HiTOP linker it invokes the STM32F10x_extsram.lsl. + + - linknor.lnk: This file is the HiTOP linker it invokes the STM32F10xnor.lsl. + + - reset_appl.scr: This file is a HiTOP script it performs a target reset. + + - reset_go_main.scr: This file is a HiTOP script and it sets the Program + Counter at the "main" instruction. + + - StartupScript.scr: This file is a HiTOP script and it performs a target + reset before loading The executable image. + + - STM32F10x_extsram.lsl: This file used to place program code (readonly) in + internal FLASH and data (readwrite, Stack and Heap) + in external SRAM. + It contains also the vector table of the STM32 high-density + devices. + You can customize this file to your need. + This file is used only with STM32 High-density devices. + + - STM32F10x_hd.lsl: This file is used to place program code (readonly) + in internal FLASH and data (readwrite, Stack and Heap) + in internal SRAM. + It contains also the vector table of the STM32 + High-Density devices. + You can customize this file to your need. + + - STM32F10xnor.lsl: This file used to place program code (readonly) in + external NOR FLASH and data (readwrite, Stack and Heap) + in internal SRAM. + It contains also the vector table of the STM32 high-density + devices. + You can customize this file to your need. + This file is used only with STM32 High-density devices. + +@par How to use it ? + +- Open the HiTOP toolchain. +- Browse to open the project.htp +- A "Download application" window is displayed, click "cancel". +- Rebuild all files: Project->Rebuild all +- Load project image : Click "ok" in the "Download application" window. +- Run the "RESET_GO_MAIN" script to set the PC at the "main" +- Run program: Debug->Go(F5). + +- When using High-density devices, it is mandatory to reset the target before + loading the project into target +- It is recommended to run the reset script ( click on TR button in the toolbar menu) + after loading the project into target. + +@note + - Low-density Value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 16 and 32 Kbytes. + - Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx + microcontrollers where the Flash memory density ranges between 16 and 32 Kbytes. + - Medium-density Value line devices are STM32F100xx microcontrollers where + the Flash memory density ranges between 64 and 128 Kbytes. + - Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx + microcontrollers where the Flash memory density ranges between 64 and 128 Kbytes. + - High-density Value line devices are STM32F100xx microcontrollers where the + Flash memory density ranges between 256 and 512 Kbytes. + - High-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 256 and 512 Kbytes. + - XL-density devices are STM32F101xx and STM32F103xx microcontrollers where + the Flash memory density ranges between 512 and 1024 Kbytes. + - Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers. + + * <h3><center>© COPYRIGHT 2011 STMicroelectronics</center></h3> + */ |