From 89d464c7f38b902e332f082f99df075dee080978 Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Sat, 29 Apr 2017 23:10:32 +0200 Subject: o Setting up for TIM1/Channel 1 as input capture. Enabling IWDG. --- stm32cubemx/Src/stm32f1xx_hal_msp.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'stm32cubemx/Src/stm32f1xx_hal_msp.c') diff --git a/stm32cubemx/Src/stm32f1xx_hal_msp.c b/stm32cubemx/Src/stm32f1xx_hal_msp.c index 696dd5d..be02361 100644 --- a/stm32cubemx/Src/stm32f1xx_hal_msp.c +++ b/stm32cubemx/Src/stm32f1xx_hal_msp.c @@ -34,6 +34,8 @@ /* Includes ------------------------------------------------------------------*/ #include "stm32f1xx_hal.h" +extern DMA_HandleTypeDef hdma_tim1_ch1; + extern void Error_Handler(void); /* USER CODE BEGIN 0 */ @@ -96,6 +98,23 @@ void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* htim_ic) GPIO_InitStruct.Pull = GPIO_NOPULL; HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + /* Peripheral DMA init*/ + + hdma_tim1_ch1.Instance = DMA1_Channel2; + hdma_tim1_ch1.Init.Direction = DMA_PERIPH_TO_MEMORY; + hdma_tim1_ch1.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_tim1_ch1.Init.MemInc = DMA_MINC_ENABLE; + hdma_tim1_ch1.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD; + hdma_tim1_ch1.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD; + hdma_tim1_ch1.Init.Mode = DMA_NORMAL; + hdma_tim1_ch1.Init.Priority = DMA_PRIORITY_LOW; + if (HAL_DMA_Init(&hdma_tim1_ch1) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(htim_ic,hdma[TIM_DMA_ID_CC1],hdma_tim1_ch1); + /* USER CODE BEGIN TIM1_MspInit 1 */ /* USER CODE END TIM1_MspInit 1 */ @@ -119,6 +138,9 @@ void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef* htim_ic) */ HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8); + /* Peripheral DMA DeInit*/ + HAL_DMA_DeInit(htim_ic->hdma[TIM_DMA_ID_CC1]); + /* Peripheral interrupt DeInit*/ HAL_NVIC_DisableIRQ(TIM1_TRG_COM_IRQn); -- cgit v1.2.3