From 067cd0ef6a7e031ea839c7d118da002267df95b3 Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Thu, 19 Jul 2018 23:00:13 +0200 Subject: wip. --- demo/doit/demo.kicad_pcb | 283 ++++++++++++++++++++++++++++++++++++++++++++++- demo/doit/demo.sch | 35 +++--- demo/doit/dodo.py | 8 +- src/ee/kicad/doit.py | 56 +++++----- test/doit/test_doit.py | 12 +- 5 files changed, 347 insertions(+), 47 deletions(-) diff --git a/demo/doit/demo.kicad_pcb b/demo/doit/demo.kicad_pcb index 02c8ecb..27217da 100644 --- a/demo/doit/demo.kicad_pcb +++ b/demo/doit/demo.kicad_pcb @@ -1 +1,282 @@ -(kicad_pcb (version 4) (host kicad "dummy file") ) +(kicad_pcb (version 20171130) (host pcbnew 5.0.0-rc3+dfsg1-2) + + (general + (thickness 1.6) + (drawings 0) + (tracks 7) + (zones 0) + (modules 3) + (nets 4) + ) + + (page A4) + (layers + (0 F.Cu signal) + (31 B.Cu signal) + (32 B.Adhes user) + (33 F.Adhes user) + (34 B.Paste user) + (35 F.Paste user) + (36 B.SilkS user) + (37 F.SilkS user) + (38 B.Mask user) + (39 F.Mask user) + (40 Dwgs.User user) + (41 Cmts.User user) + (42 Eco1.User user) + (43 Eco2.User user) + (44 Edge.Cuts user) + (45 Margin user) + (46 B.CrtYd user) + (47 F.CrtYd user) + (48 B.Fab user) + (49 F.Fab user) + ) + + (setup + (last_trace_width 0.25) + (trace_clearance 0.2) + (zone_clearance 0.508) + (zone_45_only no) + (trace_min 0.2) + (segment_width 0.2) + (edge_width 0.15) + (via_size 0.8) + (via_drill 0.4) + (via_min_size 0.4) + (via_min_drill 0.3) + (uvia_size 0.3) + (uvia_drill 0.1) + (uvias_allowed no) + (uvia_min_size 0.2) + (uvia_min_drill 0.1) + (pcb_text_width 0.3) + (pcb_text_size 1.5 1.5) + (mod_edge_width 0.15) + (mod_text_size 1 1) + (mod_text_width 0.15) + (pad_size 1.524 1.524) + (pad_drill 0.762) + (pad_to_mask_clearance 0.2) + (aux_axis_origin 0 0) + (visible_elements FFFFFF7F) + (pcbplotparams + (layerselection 0x010fc_ffffffff) + (usegerberextensions false) + (usegerberattributes false) + (usegerberadvancedattributes false) + (creategerberjobfile false) + (excludeedgelayer true) + (linewidth 0.100000) + (plotframeref false) + (viasonmask false) + (mode 1) + (useauxorigin false) + (hpglpennumber 1) + (hpglpenspeed 20) + (hpglpendiameter 15.000000) + (psnegative false) + (psa4output false) + (plotreference true) + (plotvalue true) + (plotinvisibletext false) + (padsonsilk false) + (subtractmaskfromsilk false) + (outputformat 1) + (mirror false) + (drillshape 1) + (scaleselection 1) + (outputdirectory "")) + ) + + (net 0 "") + (net 1 "Net-(BT1-Pad1)") + (net 2 GND) + (net 3 "Net-(C1-Pad1)") + + (net_class Default "This is the default net class." + (clearance 0.2) + (trace_width 0.25) + (via_dia 0.8) + (via_drill 0.4) + (uvia_dia 0.3) + (uvia_drill 0.1) + (add_net GND) + (add_net "Net-(BT1-Pad1)") + (add_net "Net-(C1-Pad1)") + ) + + (module Battery:BatteryHolder_MPD_BC2AAPC_2xAA (layer F.Cu) (tedit 5AC8F8F7) (tstamp 5B5BC36D) + (at 71.75 60.5) + (descr "2xAA cell battery holder, Memory Protection Devices P/N BC2AAPC, http://www.memoryprotectiondevices.com/datasheets/BC2AAPC-datasheet.pdf") + (tags "AA battery cell holder") + (path /5B431438) + (fp_text reference BT1 (at 26.16 -10.11) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 9V (at 26.16 23.39) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -2.84 -8.61) (end -2.84 21.89) (layer F.Fab) (width 0.1)) + (fp_line (start -2.84 21.89) (end 55.16 21.89) (layer F.Fab) (width 0.1)) + (fp_line (start 55.16 21.89) (end 55.16 -8.61) (layer F.Fab) (width 0.1)) + (fp_line (start 55.16 -8.61) (end -2.84 -8.61) (layer F.Fab) (width 0.1)) + (fp_line (start -2.94 -8.71) (end -2.94 21.99) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.94 21.99) (end 55.26 21.99) (layer F.SilkS) (width 0.12)) + (fp_line (start 55.26 21.99) (end 55.26 -8.71) (layer F.SilkS) (width 0.12)) + (fp_line (start 55.26 -8.71) (end -2.94 -8.71) (layer F.SilkS) (width 0.12)) + (fp_line (start -3.34 -9.11) (end -3.34 22.39) (layer F.CrtYd) (width 0.05)) + (fp_line (start -3.34 22.39) (end 55.66 22.39) (layer F.CrtYd) (width 0.05)) + (fp_line (start 55.66 22.39) (end 55.66 -9.11) (layer F.CrtYd) (width 0.05)) + (fp_line (start 55.66 -9.11) (end -3.34 -9.11) (layer F.CrtYd) (width 0.05)) + (fp_line (start 35.685 2.54) (end 17.905 2.54) (layer F.SilkS) (width 0.12)) + (fp_line (start 17.905 2.54) (end 17.905 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start 17.905 1.27) (end 16.635 1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start 16.635 1.27) (end 16.635 -1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start 16.635 -1.27) (end 17.905 -1.27) (layer F.SilkS) (width 0.12)) + (fp_line (start 17.905 -1.27) (end 17.905 -2.54) (layer F.SilkS) (width 0.12)) + (fp_line (start 17.905 -2.54) (end 35.685 -2.54) (layer F.SilkS) (width 0.12)) + (fp_line (start 35.685 -2.54) (end 35.685 2.54) (layer F.SilkS) (width 0.12)) + (fp_line (start 16.635 16.13) (end 34.415 16.13) (layer F.SilkS) (width 0.12)) + (fp_line (start 34.415 16.13) (end 34.415 14.86) (layer F.SilkS) (width 0.12)) + (fp_line (start 34.415 14.86) (end 35.685 14.86) (layer F.SilkS) (width 0.12)) + (fp_line (start 35.685 14.86) (end 35.685 12.32) (layer F.SilkS) (width 0.12)) + (fp_line (start 35.685 12.32) (end 34.415 12.32) (layer F.SilkS) (width 0.12)) + (fp_line (start 34.415 12.32) (end 34.415 11.05) (layer F.SilkS) (width 0.12)) + (fp_line (start 34.415 11.05) (end 16.635 11.05) (layer F.SilkS) (width 0.12)) + (fp_line (start 16.635 11.05) (end 16.635 16.13) (layer F.SilkS) (width 0.12)) + (fp_text user %R (at 26.16 6.63) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text user - (at 36.955 0) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.15))) + ) + (fp_text user + (at 15.365 0) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.15))) + ) + (fp_text user - (at 15.365 13.59) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.15))) + ) + (fp_text user + (at 36.955 13.59) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.15))) + ) + (fp_text user + (at -4.34 0) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.15))) + ) + (fp_text user - (at -4.34 13.59) (layer F.SilkS) + (effects (font (size 1.5 1.5) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0 0) (size 2.17 2.17) (drill 1.17) (layers *.Cu *.Mask) + (net 1 "Net-(BT1-Pad1)")) + (pad 2 thru_hole circle (at 0 13.59) (size 2.17 2.17) (drill 1.17) (layers *.Cu *.Mask) + (net 2 GND)) + (pad "" np_thru_hole circle (at 26.16 6.63) (size 3.65 3.65) (drill 3.65) (layers *.Cu *.Mask)) + (model ${KISYS3DMOD}/Battery.3dshapes/BatteryHolder_MPD_BC2AAPC_2xAA.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Capacitor_THT:CP_Axial_L11.0mm_D8.0mm_P15.00mm_Horizontal (layer F.Cu) (tedit 5AE50EF2) (tstamp 5B5BC1CE) + (at 46 76) + (descr "CP, Axial series, Axial, Horizontal, pin pitch=15mm, , length*diameter=11*8mm^2, Electrolytic Capacitor, , http://www.vishay.com/docs/28325/021asm.pdf") + (tags "CP Axial series Axial Horizontal pin pitch 15mm length 11mm diameter 8mm Electrolytic Capacitor") + (path /5B4314AB) + (fp_text reference C1 (at 7.5 -5.12) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 1u (at 7.5 5.12) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start 2 -4) (end 2 4) (layer F.Fab) (width 0.1)) + (fp_line (start 13 -4) (end 13 4) (layer F.Fab) (width 0.1)) + (fp_line (start 2 -4) (end 3.38 -4) (layer F.Fab) (width 0.1)) + (fp_line (start 3.38 -4) (end 4.13 -3.25) (layer F.Fab) (width 0.1)) + (fp_line (start 4.13 -3.25) (end 4.88 -4) (layer F.Fab) (width 0.1)) + (fp_line (start 4.88 -4) (end 13 -4) (layer F.Fab) (width 0.1)) + (fp_line (start 2 4) (end 3.38 4) (layer F.Fab) (width 0.1)) + (fp_line (start 3.38 4) (end 4.13 3.25) (layer F.Fab) (width 0.1)) + (fp_line (start 4.13 3.25) (end 4.88 4) (layer F.Fab) (width 0.1)) + (fp_line (start 4.88 4) (end 13 4) (layer F.Fab) (width 0.1)) + (fp_line (start 0 0) (end 2 0) (layer F.Fab) (width 0.1)) + (fp_line (start 15 0) (end 13 0) (layer F.Fab) (width 0.1)) + (fp_line (start 3.4 0) (end 4.9 0) (layer F.Fab) (width 0.1)) + (fp_line (start 4.15 -0.75) (end 4.15 0.75) (layer F.Fab) (width 0.1)) + (fp_line (start 0.13 -2.2) (end 1.63 -2.2) (layer F.SilkS) (width 0.12)) + (fp_line (start 0.88 -2.95) (end 0.88 -1.45) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.88 -4.12) (end 1.88 4.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 13.12 -4.12) (end 13.12 4.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.88 -4.12) (end 3.38 -4.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.38 -4.12) (end 4.13 -3.37) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.13 -3.37) (end 4.88 -4.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.88 -4.12) (end 13.12 -4.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.88 4.12) (end 3.38 4.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 3.38 4.12) (end 4.13 3.37) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.13 3.37) (end 4.88 4.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 4.88 4.12) (end 13.12 4.12) (layer F.SilkS) (width 0.12)) + (fp_line (start 1.24 0) (end 1.88 0) (layer F.SilkS) (width 0.12)) + (fp_line (start 13.76 0) (end 13.12 0) (layer F.SilkS) (width 0.12)) + (fp_line (start -1.25 -4.25) (end -1.25 4.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start -1.25 4.25) (end 16.25 4.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 16.25 4.25) (end 16.25 -4.25) (layer F.CrtYd) (width 0.05)) + (fp_line (start 16.25 -4.25) (end -1.25 -4.25) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 7.5 0) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (pad 1 thru_hole rect (at 0 0) (size 2 2) (drill 1) (layers *.Cu *.Mask) + (net 3 "Net-(C1-Pad1)")) + (pad 2 thru_hole oval (at 15 0) (size 2 2) (drill 1) (layers *.Cu *.Mask) + (net 2 GND)) + (model ${KISYS3DMOD}/Capacitor_THT.3dshapes/CP_Axial_L11.0mm_D8.0mm_P15.00mm_Horizontal.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (module Resistor_SMD:R_1206_3216Metric (layer F.Cu) (tedit 5B20DC38) (tstamp 5B5BC1DF) + (at 60 61.4 90) + (descr "Resistor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator") + (tags resistor) + (path /5B431328) + (attr smd) + (fp_text reference R1 (at 0 -1.82 90) (layer F.SilkS) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_text value 10k (at 0 1.82 90) (layer F.Fab) + (effects (font (size 1 1) (thickness 0.15))) + ) + (fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1)) + (fp_line (start -0.602064 -0.91) (end 0.602064 -0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -0.602064 0.91) (end 0.602064 0.91) (layer F.SilkS) (width 0.12)) + (fp_line (start -2.28 1.12) (end -2.28 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start -2.28 -1.12) (end 2.28 -1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.28 -1.12) (end 2.28 1.12) (layer F.CrtYd) (width 0.05)) + (fp_line (start 2.28 1.12) (end -2.28 1.12) (layer F.CrtYd) (width 0.05)) + (fp_text user %R (at 0 0 90) (layer F.Fab) + (effects (font (size 0.8 0.8) (thickness 0.12))) + ) + (pad 1 smd roundrect (at -1.4 0 90) (size 1.25 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2) + (net 3 "Net-(C1-Pad1)")) + (pad 2 smd roundrect (at 1.4 0 90) (size 1.25 1.75) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.2) + (net 1 "Net-(BT1-Pad1)")) + (model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_1206_3216Metric.wrl + (at (xyz 0 0 0)) + (scale (xyz 1 1 1)) + (rotate (xyz 0 0 0)) + ) + ) + + (segment (start 71.25 60) (end 71.75 60.5) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 60 60) (end 71.25 60) (width 0.25) (layer F.Cu) (net 1)) + (segment (start 62.91 74.09) (end 61 76) (width 0.25) (layer B.Cu) (net 2)) + (segment (start 71.75 74.09) (end 62.91 74.09) (width 0.25) (layer B.Cu) (net 2)) + (segment (start 60 62.8) (end 46.45 62.8) (width 0.25) (layer F.Cu) (net 3)) + (segment (start 46 63.25) (end 46 76) (width 0.25) (layer F.Cu) (net 3)) + (segment (start 46.45 62.8) (end 46 63.25) (width 0.25) (layer F.Cu) (net 3)) + +) diff --git a/demo/doit/demo.sch b/demo/doit/demo.sch index a805e83..9ccb57c 100644 --- a/demo/doit/demo.sch +++ b/demo/doit/demo.sch @@ -1,4 +1,5 @@ EESchema Schematic File Version 4 +LIBS:demo-cache EELAYER 26 0 EELAYER END $Descr A4 11693 8268 @@ -14,34 +15,34 @@ Comment3 "" Comment4 "" $EndDescr $Comp -L Device:R R? +L Device:R R1 U 1 1 5B431328 -P 4400 2600 -F 0 "R?" V 4193 2600 50 0000 C CNN -F 1 "10k" V 4284 2600 50 0000 C CNN -F 2 "" V 4330 2600 50 0001 C CNN -F 3 "~" H 4400 2600 50 0001 C CNN - 1 4400 2600 +P 4350 2600 +F 0 "R1" V 4143 2600 50 0000 C CNN +F 1 "10k" V 4234 2600 50 0000 C CNN +F 2 "Resistor_SMD:R_1206_3216Metric" V 4280 2600 50 0001 C CNN +F 3 "~" H 4350 2600 50 0001 C CNN + 1 4350 2600 0 1 1 0 $EndComp $Comp -L Device:Battery_Cell BT? +L Device:Battery_Cell BT1 U 1 1 5B431438 P 3700 2900 -F 0 "BT?" H 3818 2996 50 0000 L CNN +F 0 "BT1" H 3818 2996 50 0000 L CNN F 1 "9V" H 3818 2905 50 0000 L CNN -F 2 "" V 3700 2960 50 0001 C CNN +F 2 "Battery:BatteryHolder_MPD_BC2AAPC_2xAA" V 3700 2960 50 0001 C CNN F 3 "~" V 3700 2960 50 0001 C CNN 1 3700 2900 1 0 0 -1 $EndComp $Comp -L Device:C C? +L Device:C C1 U 1 1 5B4314AB P 5000 2850 -F 0 "C?" H 5115 2896 50 0000 L CNN +F 0 "C1" H 5115 2896 50 0000 L CNN F 1 "1u" H 5115 2805 50 0000 L CNN -F 2 "" H 5038 2700 50 0001 C CNN +F 2 "Capacitor_THT:CP_Axial_L11.0mm_D8.0mm_P15.00mm_Horizontal" H 5038 2700 50 0001 C CNN F 3 "~" H 5000 2850 50 0001 C CNN 1 5000 2850 1 0 0 -1 @@ -51,10 +52,10 @@ Wire Wire Line Wire Wire Line 5000 3100 5000 3000 $Comp -L power:GND #PWR? +L power:GND #PWR0101 U 1 1 5B4315FE P 3700 3200 -F 0 "#PWR?" H 3700 2950 50 0001 C CNN +F 0 "#PWR0101" H 3700 2950 50 0001 C CNN F 1 "GND" H 3705 3027 50 0000 C CNN F 2 "" H 3700 3200 50 0001 C CNN F 3 "" H 3700 3200 50 0001 C CNN @@ -69,9 +70,9 @@ Wire Wire Line Wire Wire Line 5000 2600 5000 2700 Wire Wire Line - 3700 2600 4250 2600 + 3700 2600 4200 2600 Wire Wire Line 3700 3100 5000 3100 Wire Wire Line - 4550 2600 5000 2600 + 4500 2600 5000 2600 $EndSCHEMATC diff --git a/demo/doit/dodo.py b/demo/doit/dodo.py index 4c8748a..a050596 100644 --- a/demo/doit/dodo.py +++ b/demo/doit/dodo.py @@ -4,11 +4,15 @@ prj = "demo" sch = "{}.sch".format(prj) kicad_pcb = "{}.kicad_pcb".format(prj) +DOIT_CONFIG = {'check_file_uptodate': 'timestamp'} + + def task_kicad(): args = { "sch": sch, "kicad_pcb": kicad_pcb, "gerber_dir": "gerber", - "components_dir": "components", + "data_set_dir": "ee", } - yield KicadDoitTasks(**args).tasks() + for t in KicadDoitTasks(**args).tasks(): + yield t diff --git a/src/ee/kicad/doit.py b/src/ee/kicad/doit.py index fcbcaef..29438ad 100644 --- a/src/ee/kicad/doit.py +++ b/src/ee/kicad/doit.py @@ -1,6 +1,5 @@ import logging import os.path -from typing import List from configclass import Config @@ -21,8 +20,12 @@ class KicadDoitTasks(object): def __init__(self, *args, **kwargs): self.config = self.config.make(kwargs) - def echo(*args, **kwargs): - logger.info("_task: args={}, kwars={}".format(args, kwargs)) + formatter = logging.Formatter("%(levelname)s: %(message)s") + ch = logging.StreamHandler() + ch.setFormatter(formatter) + logger.addHandler(ch) + + logger.setLevel(logging.DEBUG) def tasks(self, *args, **kwargs): kicad_pcb = self.config["kicad_pcb"] @@ -36,27 +39,23 @@ class KicadDoitTasks(object): if kicad_pcb and gerber_dir: tasks.append(task_kicad_gerber(kicad_pcb, gerber_dir, gerber_zip)) - sch_ds = task_kicad_sch_to_data_set(dsm, sch, - in_data_sets=[], - out_data_set="kicad-sch-data-set") \ + sch_ds = task_kicad_sch_to_data_set(dsm, sch) \ if sch else None - component_ds = task_kicad_create_component_data_set(dsm, - in_data_sets=sch_ds["targets"], - out_data_set="raw-component") \ - if sch_ds else None - - pcb_ds = task_kicad_pcb_to_data_set(dsm, kicad_pcb, in_data_sets=[], out_data_set="kicad-pcb") \ + pcb_ds = task_kicad_pcb_to_data_set(dsm, kicad_pcb) \ if kicad_pcb else None - tasks = [sch_ds, component_ds, pcb_ds] - return (t for t in tasks if t) + component_ds = task_kicad_create_component_data_set(dsm) \ + if sch_ds else None + + tasks = [component_ds, sch_ds, pcb_ds,] + return tasks def task_kicad_gerber(kicad_pcb: str, gerber_dir: str, gerber_zip: str, name="kicad-gerber"): import ee.kicad - gerber_zip = len(gerber_zip) or "{}.zip".format(gerber_dir) + gerber_zip = gerber_zip or "{}.zip".format(gerber_dir) # logger.info("gerber_zip={}".format(gerber_zip)) eg = next((p for p in (os.path.join(p, "export_gerber.py") for p in ee.kicad.__path__) if os.path.isfile(p)), None) @@ -89,8 +88,10 @@ def task_kicad_gerber(kicad_pcb: str, gerber_dir: str, gerber_zip: str, name="ki } -def task_kicad_sch_to_data_set(dsm: DataSetManager, sch, in_data_sets: List[str], out_data_set, - name="kicad-sch-to-data-set"): +def task_kicad_sch_to_data_set(dsm: DataSetManager, sch, name="kicad-sch-to-data-set"): + out_data_set = "kicad-sch" + in_data_sets = [] + def action(): import ee.kicad from ee.kicad.model import ComponentField @@ -119,21 +120,22 @@ def task_kicad_sch_to_data_set(dsm: DataSetManager, sch, in_data_sets: List[str] } -def task_kicad_pcb_to_data_set(dsm: DataSetManager, pcb_path, in_data_sets: List[str], out_data_set, - name="kicad-pcb-to-data-set"): +def task_kicad_pcb_to_data_set(dsm: DataSetManager, pcb_path, name="kicad-pcb-to-data-set"): + out_data_set = "kicad-pcb" + in_data_sets = [] + def action(): import ee.kicad.pcb from ee.kicad.pcb import FpText + logger.debug("Parsing PCB {}".format(pcb_path)) + with dsm.create_rw(out_data_set, inputs=in_data_sets) as ds: # [ds.delete(o) for o in ds.items(object_type="kicad-pcb-component")] pcb: ee.kicad.pcb.KicadPcb = ee.kicad.pcb.parse(pcb_path) for _m in pcb.modules: m: ee.kicad.pcb.Module = _m - logger.info("attrs") - for s in dir(m): - logger.info(s) o = ds.get_object("kicad-pcb-component", m.tstamp) @@ -154,10 +156,12 @@ def task_kicad_pcb_to_data_set(dsm: DataSetManager, pcb_path, in_data_sets: List } -def task_kicad_create_component_data_set(dsm: DataSetManager, in_data_sets: List[str], out_data_set, - name="kicad-create-component-data-set"): - def action(*args, **kwargs): - logger.info("args={}, kwargs={}".format(args, kwargs)) +def task_kicad_create_component_data_set(dsm: DataSetManager, name="kicad-create-component-data-set"): + out_data_set = "components" + in_data_sets = ["kicad-sch", "kicad-pcb"] + + def action(targets, *args, **kwargs): + logger.info("targets={}, args={}, kwargs={}".format(targets, args, kwargs)) with dsm.create_rw(out_data_set, inputs=in_data_sets) as ds: items = ds.items() diff --git a/test/doit/test_doit.py b/test/doit/test_doit.py index a379c97..3a0c7ec 100644 --- a/test/doit/test_doit.py +++ b/test/doit/test_doit.py @@ -1,5 +1,10 @@ +import inspect +import logging import os import os.path +from inspect import Parameter + +logger = logging.getLogger(__name__) filedir = os.path.dirname(os.path.abspath(__file__)) schematics_dir = os.path.join(filedir, "schematics") @@ -19,7 +24,12 @@ def exec_task(task): ret = os.system(cmd) assert (ret == 0) else: - a() + parameters = {} + for p in inspect.signature(a).parameters.values(): + if p.kind == Parameter.POSITIONAL_OR_KEYWORD and p.name == "targets": + parameters["targets"] = targets + + a(**parameters) def test_doit(tmpdir, caplog): -- cgit v1.2.3