o Generating mediawiki pages from Artix-7 docs.

8 files changed, 424 insertions, 0 deletions

diff --git a/Artix-7/mw/XC7A100T.mw b/Artix-7/mw/XC7A100T.mw
new file mode 100644
index 0000000..26adfd5
--- /dev/null
+++ b/Artix-7/mw/XC7A100T.mw
@@ -0,0 +1,53 @@
+= XC7A100T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A100T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::101440]]
+|-
+!Slices
+|[[Slices::15850]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::1188]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::240]]
+|-
+!18 Kb
+|[[18 Kb::270]]
+|-
+!RAM blocks
+|[[RAM blocks::135]]
+|-
+!Max
+|[[Max::4860]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::6]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::8]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::6]]
+|-
+!Max User I/O
+|[[Max User I/O::300]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw
new file mode 100644
index 0000000..7d37600
--- /dev/null
+++ b/Artix-7/mw/XC7A12T.mw
@@ -0,0 +1,53 @@
+= XC7A12T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A12T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::12800]]
+|-
+!Slices
+|[[Slices::2000]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::171]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::40]]
+|-
+!18 Kb
+|[[18 Kb::40]]
+|-
+!RAM blocks
+|[[RAM blocks::20]]
+|-
+!Max
+|[[Max::720]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::3]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::2]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::3]]
+|-
+!Max User I/O
+|[[Max User I/O::150]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A15T.mw b/Artix-7/mw/XC7A15T.mw
new file mode 100644
index 0000000..338c690
--- /dev/null
+++ b/Artix-7/mw/XC7A15T.mw
@@ -0,0 +1,53 @@
+= XC7A15T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A15T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::16640]]
+|-
+!Slices
+|[[Slices::2600]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::200]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::45]]
+|-
+!18 Kb
+|[[18 Kb::50]]
+|-
+!RAM blocks
+|[[RAM blocks::25]]
+|-
+!Max
+|[[Max::900]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::5]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::4]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::5]]
+|-
+!Max User I/O
+|[[Max User I/O::250]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A200T.mw b/Artix-7/mw/XC7A200T.mw
new file mode 100644
index 0000000..3a12e28
--- /dev/null
+++ b/Artix-7/mw/XC7A200T.mw
@@ -0,0 +1,53 @@
+= XC7A200T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A200T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::215360]]
+|-
+!Slices
+|[[Slices::33650]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::2888]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::740]]
+|-
+!18 Kb
+|[[18 Kb::730]]
+|-
+!RAM blocks
+|[[RAM blocks::365]]
+|-
+!Max
+|[[Max::13140]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::10]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::16]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::10]]
+|-
+!Max User I/O
+|[[Max User I/O::500]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A25T.mw b/Artix-7/mw/XC7A25T.mw
new file mode 100644
index 0000000..d6c6d6b
--- /dev/null
+++ b/Artix-7/mw/XC7A25T.mw
@@ -0,0 +1,53 @@
+= XC7A25T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A25T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::23360]]
+|-
+!Slices
+|[[Slices::3650]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::313]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::80]]
+|-
+!18 Kb
+|[[18 Kb::90]]
+|-
+!RAM blocks
+|[[RAM blocks::45]]
+|-
+!Max
+|[[Max::1620]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::3]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::4]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::3]]
+|-
+!Max User I/O
+|[[Max User I/O::150]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A35T.mw b/Artix-7/mw/XC7A35T.mw
new file mode 100644
index 0000000..f74f115
--- /dev/null
+++ b/Artix-7/mw/XC7A35T.mw
@@ -0,0 +1,53 @@
+= XC7A35T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A35T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::33280]]
+|-
+!Slices
+|[[Slices::5200]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::400]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::90]]
+|-
+!18 Kb
+|[[18 Kb::100]]
+|-
+!RAM blocks
+|[[RAM blocks::50]]
+|-
+!Max
+|[[Max::1800]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::5]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::4]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::5]]
+|-
+!Max User I/O
+|[[Max User I/O::250]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw
new file mode 100644
index 0000000..15b72e2
--- /dev/null
+++ b/Artix-7/mw/XC7A50T.mw
@@ -0,0 +1,53 @@
+= XC7A50T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A50T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::52160]]
+|-
+!Slices
+|[[Slices::8150]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::600]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::120]]
+|-
+!18 Kb
+|[[18 Kb::150]]
+|-
+!RAM blocks
+|[[RAM blocks::75]]
+|-
+!Max
+|[[Max::2700]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::5]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::4]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::5]]
+|-
+!Max User I/O
+|[[Max User I/O::250]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
diff --git a/Artix-7/mw/XC7A75T.mw b/Artix-7/mw/XC7A75T.mw
new file mode 100644
index 0000000..6ca4f2f
--- /dev/null
+++ b/Artix-7/mw/XC7A75T.mw
@@ -0,0 +1,53 @@
+= XC7A75T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A75T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::75520]]
+|-
+!Slices
+|[[Slices::11800]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::892]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::180]]
+|-
+!18 Kb
+|[[18 Kb::210]]
+|-
+!RAM blocks
+|[[RAM blocks::105]]
+|-
+!Max
+|[[Max::3780]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::6]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::8]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::6]]
+|-
+!Max User I/O
+|[[Max User I/O::300]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]