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-rw-r--r--Artix-7/mw.j251
-rw-r--r--Artix-7/mw/XC7A100T.mw14
-rw-r--r--Artix-7/mw/XC7A12T.mw14
-rw-r--r--Artix-7/mw/XC7A15T.mw14
-rw-r--r--Artix-7/mw/XC7A200T.mw14
-rw-r--r--Artix-7/mw/XC7A25T.mw14
-rw-r--r--Artix-7/mw/XC7A35T.mw14
-rw-r--r--Artix-7/mw/XC7A50T.mw14
-rw-r--r--Artix-7/mw/XC7A75T.mw14
-rwxr-xr-xArtix-7/run.py59
10 files changed, 119 insertions, 103 deletions
diff --git a/Artix-7/mw.j2 b/Artix-7/mw.j2
new file mode 100644
index 0000000..2ea20c0
--- /dev/null
+++ b/Artix-7/mw.j2
@@ -0,0 +1,51 @@
+= {{ part["Part number"] }} =
+
+{|class='wikitable'
+!Part number
+|[[Part number::{{ part["Part number"] }}]]
+|-
+!Logic Cells
+|[[Xilix logic cells::{{ part["Logic Cells"] }}]]
+|-
+!Slices
+|[[Slices::{{ part["Slices"] }}]]
+|-
+!Distributed RAM
+|[[Distributed RAM::{{ part["Max Distributed RAM (Kb)"] }} kB]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::{{ part["DSP48E1 Slices"] }}]]
+|-
+!RAM blocks
+|[[RAM blocks::{{ part["36 Kb"] }}]]
+|-
+!RAM
+|[[RAM::{{ part["Max (Kb)"] }} kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::{{ part["CMTs"] }}]]
+|-
+!PCIe
+|[[PCIe::{{ part["PCIe"] }}]]
+|-
+!GTPs
+|[[GTPs::{{ part["GTPs"] }}]]
+|-
+!XADC Blocks
+|[[XADC Blocks::{{ part["XADC Blocks"] }}]]
+|-
+!IO banks
+|[[IO banks::{{ part["Total I/O Banks"] }}]]
+|-
+!Available IO
+|[[Available IO::{{ part["Max User I/O"] }}]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
+
diff --git a/Artix-7/mw/XC7A100T.mw b/Artix-7/mw/XC7A100T.mw
index c7ff7d1..1eca9ee 100644
--- a/Artix-7/mw/XC7A100T.mw
+++ b/Artix-7/mw/XC7A100T.mw
@@ -11,7 +11,7 @@
|[[Slices::15850]]
|-
!Distributed RAM
-|[[Distributed RAM::1188]]
+|[[Distributed RAM::1188 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::240]]
@@ -20,10 +20,10 @@
|[[RAM blocks::135]]
|-
!RAM
-|[[RAM::4860]]
+|[[RAM::4860 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::6]]
+|[[Xilix clock management tiles::6]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::6]]
|-
-!Max User I/O
-|[[Max User I/O::300]]
+!Available IO
+|[[Available IO::300]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw
index 5e3006c..1a13879 100644
--- a/Artix-7/mw/XC7A12T.mw
+++ b/Artix-7/mw/XC7A12T.mw
@@ -11,7 +11,7 @@
|[[Slices::2000]]
|-
!Distributed RAM
-|[[Distributed RAM::171]]
+|[[Distributed RAM::171 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::40]]
@@ -20,10 +20,10 @@
|[[RAM blocks::20]]
|-
!RAM
-|[[RAM::720]]
+|[[RAM::720 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::3]]
+|[[Xilix clock management tiles::3]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::3]]
|-
-!Max User I/O
-|[[Max User I/O::150]]
+!Available IO
+|[[Available IO::150]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A15T.mw b/Artix-7/mw/XC7A15T.mw
index 368ff22..15e7175 100644
--- a/Artix-7/mw/XC7A15T.mw
+++ b/Artix-7/mw/XC7A15T.mw
@@ -11,7 +11,7 @@
|[[Slices::2600]]
|-
!Distributed RAM
-|[[Distributed RAM::200]]
+|[[Distributed RAM::200 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::45]]
@@ -20,10 +20,10 @@
|[[RAM blocks::25]]
|-
!RAM
-|[[RAM::900]]
+|[[RAM::900 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::5]]
+|[[Xilix clock management tiles::5]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::5]]
|-
-!Max User I/O
-|[[Max User I/O::250]]
+!Available IO
+|[[Available IO::250]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A200T.mw b/Artix-7/mw/XC7A200T.mw
index d031550..1b7b819 100644
--- a/Artix-7/mw/XC7A200T.mw
+++ b/Artix-7/mw/XC7A200T.mw
@@ -11,7 +11,7 @@
|[[Slices::33650]]
|-
!Distributed RAM
-|[[Distributed RAM::2888]]
+|[[Distributed RAM::2888 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::740]]
@@ -20,10 +20,10 @@
|[[RAM blocks::365]]
|-
!RAM
-|[[RAM::13140]]
+|[[RAM::13140 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::10]]
+|[[Xilix clock management tiles::10]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::10]]
|-
-!Max User I/O
-|[[Max User I/O::500]]
+!Available IO
+|[[Available IO::500]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A25T.mw b/Artix-7/mw/XC7A25T.mw
index 182651d..78ffda6 100644
--- a/Artix-7/mw/XC7A25T.mw
+++ b/Artix-7/mw/XC7A25T.mw
@@ -11,7 +11,7 @@
|[[Slices::3650]]
|-
!Distributed RAM
-|[[Distributed RAM::313]]
+|[[Distributed RAM::313 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::80]]
@@ -20,10 +20,10 @@
|[[RAM blocks::45]]
|-
!RAM
-|[[RAM::1620]]
+|[[RAM::1620 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::3]]
+|[[Xilix clock management tiles::3]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::3]]
|-
-!Max User I/O
-|[[Max User I/O::150]]
+!Available IO
+|[[Available IO::150]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A35T.mw b/Artix-7/mw/XC7A35T.mw
index b5a0cde..89a3c3b 100644
--- a/Artix-7/mw/XC7A35T.mw
+++ b/Artix-7/mw/XC7A35T.mw
@@ -11,7 +11,7 @@
|[[Slices::5200]]
|-
!Distributed RAM
-|[[Distributed RAM::400]]
+|[[Distributed RAM::400 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::90]]
@@ -20,10 +20,10 @@
|[[RAM blocks::50]]
|-
!RAM
-|[[RAM::1800]]
+|[[RAM::1800 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::5]]
+|[[Xilix clock management tiles::5]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::5]]
|-
-!Max User I/O
-|[[Max User I/O::250]]
+!Available IO
+|[[Available IO::250]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw
index f8b5e1b..48b575f 100644
--- a/Artix-7/mw/XC7A50T.mw
+++ b/Artix-7/mw/XC7A50T.mw
@@ -11,7 +11,7 @@
|[[Slices::8150]]
|-
!Distributed RAM
-|[[Distributed RAM::600]]
+|[[Distributed RAM::600 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::120]]
@@ -20,10 +20,10 @@
|[[RAM blocks::75]]
|-
!RAM
-|[[RAM::2700]]
+|[[RAM::2700 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::5]]
+|[[Xilix clock management tiles::5]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::5]]
|-
-!Max User I/O
-|[[Max User I/O::250]]
+!Available IO
+|[[Available IO::250]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/mw/XC7A75T.mw b/Artix-7/mw/XC7A75T.mw
index 429684c..0a20722 100644
--- a/Artix-7/mw/XC7A75T.mw
+++ b/Artix-7/mw/XC7A75T.mw
@@ -11,7 +11,7 @@
|[[Slices::11800]]
|-
!Distributed RAM
-|[[Distributed RAM::892]]
+|[[Distributed RAM::892 kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::180]]
@@ -20,10 +20,10 @@
|[[RAM blocks::105]]
|-
!RAM
-|[[RAM::3780]]
+|[[RAM::3780 kB]]
|-
!Clock management tiles
-|[[Xilix Clock management tiles::6]]
+|[[Xilix clock management tiles::6]]
|-
!PCIe
|[[PCIe::1]]
@@ -37,11 +37,11 @@
!IO banks
|[[IO banks::6]]
|-
-!Max User I/O
-|[[Max User I/O::300]]
+!Available IO
+|[[Available IO::300]]
|-
-!RAM Block Size
-|[[RAM Block Size::36 kB]]
+!RAM block size
+|[[RAM block size::36 kB]]
|-
|}
diff --git a/Artix-7/run.py b/Artix-7/run.py
index 7b1c5a8..f436b37 100755
--- a/Artix-7/run.py
+++ b/Artix-7/run.py
@@ -1,29 +1,19 @@
#!/usr/bin/env python3
-import shutil
import csv
import os
import re
+import shutil
import sys
-from pathlib import Path
-from itertools import groupby
from collections import defaultdict, namedtuple
+from itertools import groupby
+from jinja2 import Environment, FileSystemLoader, select_autoescape
+from pathlib import Path
-field_skip = set([
- "18 Kb",
-])
-field_mapping = {
- "36 Kb": ("RAM blocks", None),
- "Max Distributed RAM (Kb)": ("Distributed RAM", None),
- "Max (Kb)": ("RAM", None),
- "Total I/O Banks": ("IO banks", None),
- "Logic Cells": (None, "Xilix logic cells"),
- "CMTs": ("Clock management tiles", "Xilix Clock management tiles"),
-}
-
-extra_fields = {
- "RAM Block Size": "36 kB"
-}
+env = Environment(
+ loader=FileSystemLoader("."),
+ autoescape=select_autoescape(['html', 'xml'])
+)
def index_by_header(rows):
item_keys = rows[0]
@@ -131,35 +121,10 @@ with open("parts.csv") as f:
for part in parts.values():
part_number = part["Part number"]
- for k, v in extra_fields.items():
- part[k] = v
-
print("--- PART: {} ---".format(part_number))
path = out_dir / "{}.mw".format(part_number)
with open(path, "w") as out:
- p = lambda s = None: print(s if s is not None else "", file=out)
- def field(k, v):
- pass
-
- p("= {} =".format(part_number))
- p()
- p("{|class='wikitable'")
- for field, value in part.items():
- if field in field_skip:
- continue
-
- mapping = field_mapping.get(field)
- f = field
- if mapping is not None:
- field = mapping[0] if mapping[0] else field
- f = mapping[1] if mapping[1] else field
-
- p("!{}".format(field))
- p("|[[{}::{}]]".format(f, value))
- p("|-")
- p("|}")
-
- p()
- p("[[Category:Generated]]")
- p("[[Category:FPGA Chip]]")
- p("[[Category:Artix-7 generated data set]]")
+ template = env.get_template("mw.j2")
+ out.write(template.render(part=part))
+ for field in part:
+ print(field)
generated by cgit v1.2.3 (git 2.46.0) at 2024-12-22 21:22:02 +0000