summaryrefslogtreecommitdiff
path: root/Kintex-7/mw/Chip:XC7K480T.mw
diff options
context:
space:
mode:
Diffstat (limited to 'Kintex-7/mw/Chip:XC7K480T.mw')
-rw-r--r--Kintex-7/mw/Chip:XC7K480T.mw43
1 files changed, 43 insertions, 0 deletions
diff --git a/Kintex-7/mw/Chip:XC7K480T.mw b/Kintex-7/mw/Chip:XC7K480T.mw
new file mode 100644
index 0000000..b5a1bf3
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K480T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::477760]]
+|-
+!Slices
+|[[Xilix 7 series slices::74650]]
+|-
+!Distributed RAM
+|[[Distributed RAM::6788 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::955]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::34380 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::8]]
+|-
+!Available IO
+|[[Available IO::400]]
+|-
+!IO banks
+|[[IO banks::8]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;32]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]