From 06e395bc68e7d959a43d583f5e481e3ab4f093bf Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Mon, 13 Aug 2018 21:51:37 +0200 Subject: o Fixing field_skip, better note regex. --- Artix-7/mw/XC7A100T.mw | 11 ++++------- Artix-7/mw/XC7A12T.mw | 11 ++++------- Artix-7/mw/XC7A15T.mw | 11 ++++------- Artix-7/mw/XC7A200T.mw | 11 ++++------- Artix-7/mw/XC7A25T.mw | 11 ++++------- Artix-7/mw/XC7A35T.mw | 11 ++++------- Artix-7/mw/XC7A50T.mw | 11 ++++------- Artix-7/mw/XC7A75T.mw | 11 ++++------- Artix-7/run.py | 9 +++++---- 9 files changed, 37 insertions(+), 60 deletions(-) diff --git a/Artix-7/mw/XC7A100T.mw b/Artix-7/mw/XC7A100T.mw index 26adfd5..c7ff7d1 100644 --- a/Artix-7/mw/XC7A100T.mw +++ b/Artix-7/mw/XC7A100T.mw @@ -10,20 +10,17 @@ !Slices |[[Slices::15850]] |- -!Max Distributed RAM -|[[Max Distributed RAM::1188]] +!Distributed RAM +|[[Distributed RAM::1188]] |- !DSP48E1 Slices |[[DSP48E1 Slices::240]] |- -!18 Kb -|[[18 Kb::270]] -|- !RAM blocks |[[RAM blocks::135]] |- -!Max -|[[Max::4860]] +!RAM +|[[RAM::4860]] |- !Clock management tiles |[[Xilix Clock management tiles::6]] diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw index 7d37600..5e3006c 100644 --- a/Artix-7/mw/XC7A12T.mw +++ b/Artix-7/mw/XC7A12T.mw @@ -10,20 +10,17 @@ !Slices |[[Slices::2000]] |- -!Max Distributed RAM -|[[Max Distributed RAM::171]] +!Distributed RAM +|[[Distributed RAM::171]] |- !DSP48E1 Slices |[[DSP48E1 Slices::40]] |- -!18 Kb -|[[18 Kb::40]] -|- !RAM blocks |[[RAM blocks::20]] |- -!Max -|[[Max::720]] +!RAM +|[[RAM::720]] |- !Clock management tiles |[[Xilix Clock management tiles::3]] diff --git a/Artix-7/mw/XC7A15T.mw b/Artix-7/mw/XC7A15T.mw index 338c690..368ff22 100644 --- a/Artix-7/mw/XC7A15T.mw +++ b/Artix-7/mw/XC7A15T.mw @@ -10,20 +10,17 @@ !Slices |[[Slices::2600]] |- -!Max Distributed RAM -|[[Max Distributed RAM::200]] +!Distributed RAM +|[[Distributed RAM::200]] |- !DSP48E1 Slices |[[DSP48E1 Slices::45]] |- -!18 Kb -|[[18 Kb::50]] -|- !RAM blocks |[[RAM blocks::25]] |- -!Max -|[[Max::900]] +!RAM +|[[RAM::900]] |- !Clock management tiles |[[Xilix Clock management tiles::5]] diff --git a/Artix-7/mw/XC7A200T.mw b/Artix-7/mw/XC7A200T.mw index 3a12e28..d031550 100644 --- a/Artix-7/mw/XC7A200T.mw +++ b/Artix-7/mw/XC7A200T.mw @@ -10,20 +10,17 @@ !Slices |[[Slices::33650]] |- -!Max Distributed RAM -|[[Max Distributed RAM::2888]] +!Distributed RAM +|[[Distributed RAM::2888]] |- !DSP48E1 Slices |[[DSP48E1 Slices::740]] |- -!18 Kb -|[[18 Kb::730]] -|- !RAM blocks |[[RAM blocks::365]] |- -!Max -|[[Max::13140]] +!RAM +|[[RAM::13140]] |- !Clock management tiles |[[Xilix Clock management tiles::10]] diff --git a/Artix-7/mw/XC7A25T.mw b/Artix-7/mw/XC7A25T.mw index d6c6d6b..182651d 100644 --- a/Artix-7/mw/XC7A25T.mw +++ b/Artix-7/mw/XC7A25T.mw @@ -10,20 +10,17 @@ !Slices |[[Slices::3650]] |- -!Max Distributed RAM -|[[Max Distributed RAM::313]] +!Distributed RAM +|[[Distributed RAM::313]] |- !DSP48E1 Slices |[[DSP48E1 Slices::80]] |- -!18 Kb -|[[18 Kb::90]] -|- !RAM blocks |[[RAM blocks::45]] |- -!Max -|[[Max::1620]] +!RAM +|[[RAM::1620]] |- !Clock management tiles |[[Xilix Clock management tiles::3]] diff --git a/Artix-7/mw/XC7A35T.mw b/Artix-7/mw/XC7A35T.mw index f74f115..b5a0cde 100644 --- a/Artix-7/mw/XC7A35T.mw +++ b/Artix-7/mw/XC7A35T.mw @@ -10,20 +10,17 @@ !Slices |[[Slices::5200]] |- -!Max Distributed RAM -|[[Max Distributed RAM::400]] +!Distributed RAM +|[[Distributed RAM::400]] |- !DSP48E1 Slices |[[DSP48E1 Slices::90]] |- -!18 Kb -|[[18 Kb::100]] -|- !RAM blocks |[[RAM blocks::50]] |- -!Max -|[[Max::1800]] +!RAM +|[[RAM::1800]] |- !Clock management tiles |[[Xilix Clock management tiles::5]] diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw index 15b72e2..f8b5e1b 100644 --- a/Artix-7/mw/XC7A50T.mw +++ b/Artix-7/mw/XC7A50T.mw @@ -10,20 +10,17 @@ !Slices |[[Slices::8150]] |- -!Max Distributed RAM -|[[Max Distributed RAM::600]] +!Distributed RAM +|[[Distributed RAM::600]] |- !DSP48E1 Slices |[[DSP48E1 Slices::120]] |- -!18 Kb -|[[18 Kb::150]] -|- !RAM blocks |[[RAM blocks::75]] |- -!Max -|[[Max::2700]] +!RAM +|[[RAM::2700]] |- !Clock management tiles |[[Xilix Clock management tiles::5]] diff --git a/Artix-7/mw/XC7A75T.mw b/Artix-7/mw/XC7A75T.mw index 6ca4f2f..429684c 100644 --- a/Artix-7/mw/XC7A75T.mw +++ b/Artix-7/mw/XC7A75T.mw @@ -10,20 +10,17 @@ !Slices |[[Slices::11800]] |- -!Max Distributed RAM -|[[Max Distributed RAM::892]] +!Distributed RAM +|[[Distributed RAM::892]] |- !DSP48E1 Slices |[[DSP48E1 Slices::180]] |- -!18 Kb -|[[18 Kb::210]] -|- !RAM blocks |[[RAM blocks::105]] |- -!Max -|[[Max::3780]] +!RAM +|[[RAM::3780]] |- !Clock management tiles |[[Xilix Clock management tiles::6]] diff --git a/Artix-7/run.py b/Artix-7/run.py index 6a42383..7b1c5a8 100755 --- a/Artix-7/run.py +++ b/Artix-7/run.py @@ -9,11 +9,12 @@ from pathlib import Path from itertools import groupby from collections import defaultdict, namedtuple -field_skip = set( +field_skip = set([ "18 Kb", -) +]) field_mapping = { "36 Kb": ("RAM blocks", None), + "Max Distributed RAM (Kb)": ("Distributed RAM", None), "Max (Kb)": ("RAM", None), "Total I/O Banks": ("IO banks", None), "Logic Cells": (None, "Xilix logic cells"), @@ -56,7 +57,7 @@ def table_to_map(table, keys_in: str = None): def read_csv(f, remove_notes = True): table = [row for row in csv.reader(f) if not row[0].startswith("#") and len(row[0]) > 0] if remove_notes: - r = r"\(.*\)" + r = r"\([0-9]+\)" table[0] = [re.sub(r, "", name) for name in table[0]] table[0] = [name.strip() for name in table[0]] return table @@ -89,7 +90,7 @@ with open("package-devices.csv") as f: # for r in rows: # print(r) - r = r"\(.*\)" + r = r"\([0-9]+\)" package_idx = {int(idx): re.sub(r, "", part) for idx, part in enumerate(rows[0]) if len(part) and idx > 0} io_by_part = {} -- cgit v1.2.3