From 07a64e370e06603c9702e93e6b54540b320c2cda Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Mon, 13 Aug 2018 20:46:09 +0200 Subject: o Generating mediawiki pages from Artix-7 docs. --- .gitignore | 1 + Artix-7/Artix-7 FPGAs.ods | Bin 0 -> 12856 bytes Artix-7/README.md | 1 + Artix-7/mw/XC7A100T.mw | 53 +++++++++++++ Artix-7/mw/XC7A12T.mw | 53 +++++++++++++ Artix-7/mw/XC7A15T.mw | 53 +++++++++++++ Artix-7/mw/XC7A200T.mw | 53 +++++++++++++ Artix-7/mw/XC7A25T.mw | 53 +++++++++++++ Artix-7/mw/XC7A35T.mw | 53 +++++++++++++ Artix-7/mw/XC7A50T.mw | 53 +++++++++++++ Artix-7/mw/XC7A75T.mw | 53 +++++++++++++ Artix-7/package-devices.csv | 25 ++++++ Artix-7/packages.csv | 12 +++ Artix-7/parts.csv | 22 ++++++ Artix-7/run.py | 164 ++++++++++++++++++++++++++++++++++++++++ Artix-7/temperatures.csv | 5 ++ docs/ds180_7Series_Overview.pdf | Bin 0 -> 456818 bytes 17 files changed, 654 insertions(+) create mode 100644 .gitignore create mode 100644 Artix-7/Artix-7 FPGAs.ods create mode 100644 Artix-7/README.md create mode 100644 Artix-7/mw/XC7A100T.mw create mode 100644 Artix-7/mw/XC7A12T.mw create mode 100644 Artix-7/mw/XC7A15T.mw create mode 100644 Artix-7/mw/XC7A200T.mw create mode 100644 Artix-7/mw/XC7A25T.mw create mode 100644 Artix-7/mw/XC7A35T.mw create mode 100644 Artix-7/mw/XC7A50T.mw create mode 100644 Artix-7/mw/XC7A75T.mw create mode 100644 Artix-7/package-devices.csv create mode 100644 Artix-7/packages.csv create mode 100644 Artix-7/parts.csv create mode 100755 Artix-7/run.py create mode 100644 Artix-7/temperatures.csv create mode 100644 docs/ds180_7Series_Overview.pdf diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..63cf315 --- /dev/null +++ b/.gitignore @@ -0,0 +1 @@ +.~* diff --git a/Artix-7/Artix-7 FPGAs.ods b/Artix-7/Artix-7 FPGAs.ods new file mode 100644 index 0000000..e6505f2 Binary files /dev/null and b/Artix-7/Artix-7 FPGAs.ods differ diff --git a/Artix-7/README.md b/Artix-7/README.md new file mode 100644 index 0000000..779f0f6 --- /dev/null +++ b/Artix-7/README.md @@ -0,0 +1 @@ +Data taken from ds180_7Series_Overview.pdf. diff --git a/Artix-7/mw/XC7A100T.mw b/Artix-7/mw/XC7A100T.mw new file mode 100644 index 0000000..26adfd5 --- /dev/null +++ b/Artix-7/mw/XC7A100T.mw @@ -0,0 +1,53 @@ += XC7A100T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A100T]] +|- +!Logic Cells +|[[Xilix logic cells::101440]] +|- +!Slices +|[[Slices::15850]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::1188]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::240]] +|- +!18 Kb +|[[18 Kb::270]] +|- +!RAM blocks +|[[RAM blocks::135]] +|- +!Max +|[[Max::4860]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::6]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::8]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::6]] +|- +!Max User I/O +|[[Max User I/O::300]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw new file mode 100644 index 0000000..7d37600 --- /dev/null +++ b/Artix-7/mw/XC7A12T.mw @@ -0,0 +1,53 @@ += XC7A12T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A12T]] +|- +!Logic Cells +|[[Xilix logic cells::12800]] +|- +!Slices +|[[Slices::2000]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::171]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::40]] +|- +!18 Kb +|[[18 Kb::40]] +|- +!RAM blocks +|[[RAM blocks::20]] +|- +!Max +|[[Max::720]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::3]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::2]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::3]] +|- +!Max User I/O +|[[Max User I/O::150]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A15T.mw b/Artix-7/mw/XC7A15T.mw new file mode 100644 index 0000000..338c690 --- /dev/null +++ b/Artix-7/mw/XC7A15T.mw @@ -0,0 +1,53 @@ += XC7A15T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A15T]] +|- +!Logic Cells +|[[Xilix logic cells::16640]] +|- +!Slices +|[[Slices::2600]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::200]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::45]] +|- +!18 Kb +|[[18 Kb::50]] +|- +!RAM blocks +|[[RAM blocks::25]] +|- +!Max +|[[Max::900]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::5]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::4]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::5]] +|- +!Max User I/O +|[[Max User I/O::250]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A200T.mw b/Artix-7/mw/XC7A200T.mw new file mode 100644 index 0000000..3a12e28 --- /dev/null +++ b/Artix-7/mw/XC7A200T.mw @@ -0,0 +1,53 @@ += XC7A200T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A200T]] +|- +!Logic Cells +|[[Xilix logic cells::215360]] +|- +!Slices +|[[Slices::33650]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::2888]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::740]] +|- +!18 Kb +|[[18 Kb::730]] +|- +!RAM blocks +|[[RAM blocks::365]] +|- +!Max +|[[Max::13140]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::10]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::16]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::10]] +|- +!Max User I/O +|[[Max User I/O::500]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A25T.mw b/Artix-7/mw/XC7A25T.mw new file mode 100644 index 0000000..d6c6d6b --- /dev/null +++ b/Artix-7/mw/XC7A25T.mw @@ -0,0 +1,53 @@ += XC7A25T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A25T]] +|- +!Logic Cells +|[[Xilix logic cells::23360]] +|- +!Slices +|[[Slices::3650]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::313]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::80]] +|- +!18 Kb +|[[18 Kb::90]] +|- +!RAM blocks +|[[RAM blocks::45]] +|- +!Max +|[[Max::1620]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::3]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::4]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::3]] +|- +!Max User I/O +|[[Max User I/O::150]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A35T.mw b/Artix-7/mw/XC7A35T.mw new file mode 100644 index 0000000..f74f115 --- /dev/null +++ b/Artix-7/mw/XC7A35T.mw @@ -0,0 +1,53 @@ += XC7A35T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A35T]] +|- +!Logic Cells +|[[Xilix logic cells::33280]] +|- +!Slices +|[[Slices::5200]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::400]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::90]] +|- +!18 Kb +|[[18 Kb::100]] +|- +!RAM blocks +|[[RAM blocks::50]] +|- +!Max +|[[Max::1800]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::5]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::4]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::5]] +|- +!Max User I/O +|[[Max User I/O::250]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw new file mode 100644 index 0000000..15b72e2 --- /dev/null +++ b/Artix-7/mw/XC7A50T.mw @@ -0,0 +1,53 @@ += XC7A50T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A50T]] +|- +!Logic Cells +|[[Xilix logic cells::52160]] +|- +!Slices +|[[Slices::8150]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::600]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::120]] +|- +!18 Kb +|[[18 Kb::150]] +|- +!RAM blocks +|[[RAM blocks::75]] +|- +!Max +|[[Max::2700]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::5]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::4]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::5]] +|- +!Max User I/O +|[[Max User I/O::250]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A75T.mw b/Artix-7/mw/XC7A75T.mw new file mode 100644 index 0000000..6ca4f2f --- /dev/null +++ b/Artix-7/mw/XC7A75T.mw @@ -0,0 +1,53 @@ += XC7A75T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A75T]] +|- +!Logic Cells +|[[Xilix logic cells::75520]] +|- +!Slices +|[[Slices::11800]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::892]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::180]] +|- +!18 Kb +|[[18 Kb::210]] +|- +!RAM blocks +|[[RAM blocks::105]] +|- +!Max +|[[Max::3780]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::6]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::8]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::6]] +|- +!Max User I/O +|[[Max User I/O::300]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/package-devices.csv b/Artix-7/package-devices.csv new file mode 100644 index 0000000..7014f4d --- /dev/null +++ b/Artix-7/package-devices.csv @@ -0,0 +1,25 @@ +#,Table 5: Artix-7 FPGA Device-Package Combinations and Maximum I/Os,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,, +Package(1),CPG236,,CPG238,,CSG324,,CSG325,,FTG256,,SBG484,,FGG484(2),,FBG484(2),,FGG676(3),,FBG676(3),,FFG1156, +,,,,,,,,,,,,,,,,,,,,,, +XC7A12T,,,2,112,2,150,,,,,,,,,,,,,,,, +XC7A15T,2,106,,,0,210,4,150,0,170,,,4,250,,,,,,,, +XC7A25T,,,2,112,,,4,150,,,,,,,,,,,,,, +XC7A35T,2,106,,,0,210,4,150,0,170,,,4,250,,,,,,,, +XC7A50T,2,106,,,0,210,4,150,0,170,,,4,250,,,,,,,, +XC7A75T,,,,,0,210,,,0,170,,,4,285,,,8,300,,,, +XC7A100T,,,,,0,210,,,0,170,,,4,285,,,8,300,,,, +XC7A200T,,,,,,,,,,,4,285,,,4,285,,,8,400,16,500 +,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,, +,,,,,,,,,,,,,,,,,,,,,, +# ,Notes:,,,,,,,,,,,,,,,,,,,,, +# ,"1. All packages listed are Pb-free (SBG, FBG, FFG with exemption 15). Some packages are available in Pb option.",,,,,,,,,,,,,,,,,,,,, +# ,2. Devices in FGG484 and FBG484 are footprint compatible.,,,,,,,,,,,,,,,,,,,,, +# ,3. Devices in FGG676 and FBG676 are footprint compatible.,,,,,,,,,,,,,,,,,,,,, +# ,"4. GTP transceivers in CP, CS, FT, and FG packages support data rates up to 6.25 Gb/s.",,,,,,,,,,,,,,,,,,,,, +# ,5. HR = High-range I/O with support for I/O voltage from 1.2V to 3.3V.,,,,,,,,,,,,,,,,,,,,, diff --git a/Artix-7/packages.csv b/Artix-7/packages.csv new file mode 100644 index 0000000..b5ed805 --- /dev/null +++ b/Artix-7/packages.csv @@ -0,0 +1,12 @@ +Package,Dimensions,Ball Pitch +CPG236,10,0.5 +CPG238,10,0.5 +CSG324,15,0.8 +CSG325,15,0.8 +FTG256,17,1 +SBG484,19,0.8 +FGG484,23,1 +FBG484,23,1 +FGG676,27,1 +FBG676,27,1 +FFG1156,35,1 diff --git a/Artix-7/parts.csv b/Artix-7/parts.csv new file mode 100644 index 0000000..5b0aaf0 --- /dev/null +++ b/Artix-7/parts.csv @@ -0,0 +1,22 @@ +#,Table 4: Artix-7 FPGA Feature Summary by Device,,,,,,,,,,,, +Part number,Logic Cells,Slices(1),Max Distributed RAM (Kb),DSP48E1 Slices(2),18 Kb,36 Kb,Max (Kb),CMTs(4),PCIe(5),GTPs,XADC Blocks,Total I/O Banks(6),Max User I/O(7) +XC7A12T,12800,2000,171,40,40,20,720,3,1,2,1,3,150 +XC7A15T,16640,2600,200,45,50,25,900,5,1,4,1,5,250 +XC7A25T,23360,3650,313,80,90,45,1620,3,1,4,1,3,150 +XC7A35T,33280,5200,400,90,100,50,1800,5,1,4,1,5,250 +XC7A50T,52160,8150,600,120,150,75,2700,5,1,4,1,5,250 +XC7A75T,75520,11800,892,180,210,105,3780,6,1,8,1,6,300 +XC7A100T,101440,15850,1188,240,270,135,4860,6,1,8,1,6,300 +XC7A200T,215360,33650,2888,740,730,365,13140,10,1,16,1,10,500 +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +,,,,,,,,,,,,, +#,Notes:,,,,,,,,,,,, +#,1. Each 7 series FPGA slice contains four LUTs and eight flip-flops; only some slices can use their LUTs as distributed RAM or SRLs.,,,,,,,,,,,, +#,"2. Each DSP slice contains a pre-adder, a 25 x 18 multiplier, an adder, and an accumulator.",,,,,,,,,,,, +#,3. Block RAMs are fundamentally 36 Kb in size; each block can also be used as two independent 18 Kb blocks.,,,,,,,,,,,, +#,4. Each CMT contains one MMCM and one PLL.,,,,,,,,,,,, +#,5. Artix-7 FPGA Interface Blocks for PCI Express support up to x4 Gen 2.,,,,,,,,,,,, +#,6. Does not include configuration Bank 0.,,,,,,,,,,,, +#,7. This number does not include GTP transceivers.,,,,,,,,,,,, diff --git a/Artix-7/run.py b/Artix-7/run.py new file mode 100755 index 0000000..6a42383 --- /dev/null +++ b/Artix-7/run.py @@ -0,0 +1,164 @@ +#!/usr/bin/env python3 + +import shutil +import csv +import os +import re +import sys +from pathlib import Path +from itertools import groupby +from collections import defaultdict, namedtuple + +field_skip = set( + "18 Kb", +) +field_mapping = { + "36 Kb": ("RAM blocks", None), + "Max (Kb)": ("RAM", None), + "Total I/O Banks": ("IO banks", None), + "Logic Cells": (None, "Xilix logic cells"), + "CMTs": ("Clock management tiles", "Xilix Clock management tiles"), +} + +extra_fields = { + "RAM Block Size": "36 kB" +} + +def index_by_header(rows): + item_keys = rows[0] + items = {k: {} for idx, k in enumerate(item_keys) if idx > 0} + fields = set() + for r_idx, row in enumerate(rows): + for c_idx, cell in enumerate(row): + if c_idx == 0: + field = cell + fields.add(field) + else: + key = item_keys[c_idx] + item = items[key] + item[field] = cell + return fields, items + +def table_to_map(table, keys_in: str = None): + if keys_in == "rows": + data = {} + fields = table[0] + for row in table[1:]: + key = row[0] + data[key] = o = {} + for idx, cell in enumerate(row): + field = fields[idx] + o[field] = cell + return data + else: + raise Exception("unknown keys_in value: {}".format(keys_in)) + +def read_csv(f, remove_notes = True): + table = [row for row in csv.reader(f) if not row[0].startswith("#") and len(row[0]) > 0] + if remove_notes: + r = r"\(.*\)" + table[0] = [re.sub(r, "", name) for name in table[0]] + table[0] = [name.strip() for name in table[0]] + return table + +dbg = lambda x: '' +dbg = print +p = print + +with open("temperatures.csv") as f: + rows = list(csv.reader(f)) + Temperature = namedtuple("Temperature", rows[0]) + temperatures = {row[0]: Temperature(*row) for row in rows[1:]} + +print("Temperatures") +for t in temperatures.values(): + print(t) + +with open("packages.csv") as f: + rows = list(csv.reader(f)) + Package = namedtuple("Package", [r.lower().replace(" ", "_") for r in rows[0]]) + packages = [Package(*r) for r in rows[1:]] + +print("Packages") +for p in packages: + print(p) + +with open("package-devices.csv") as f: + rows = read_csv(f) + +# for r in rows: +# print(r) + + r = r"\(.*\)" + package_idx = {int(idx): re.sub(r, "", part) for idx, part in enumerate(rows[0]) if len(part) and idx > 0} + + io_by_part = {} + for row in rows[1:]: + part = row[0] + io_by_part[part] = info = {} + + for idx, package in package_idx.items(): + transceivers = row[idx] + if len(transceivers) == 0: + continue + pins = row[idx + 1] + info[package] = (package, pins, transceivers) +# print("package={}, pins={}, tx={}".format(package, pins, transceivers)) + +print("IO") +for part, info in io_by_part.items(): + print(part) + for package, pins, tx in info.values(): + print(" {}: pins: {}, transceivers: {}".format(package, pins, tx)) + +if False: + sys.exit(1) + +with open("parts.csv") as f: + table = read_csv(f) + parts = table_to_map(table, keys_in="rows") + + out_dir = Path("mw") + if out_dir.exists(): + shutil.rmtree(out_dir) + out_dir.mkdir() + +# print("parts") +# for part, info in rows.items(): +# print(info) + + for part in parts.values(): + part_number = part["Part number"] + + for k, v in extra_fields.items(): + part[k] = v + + print("--- PART: {} ---".format(part_number)) + path = out_dir / "{}.mw".format(part_number) + with open(path, "w") as out: + p = lambda s = None: print(s if s is not None else "", file=out) + def field(k, v): + pass + + p("= {} =".format(part_number)) + p() + p("{|class='wikitable'") + for field, value in part.items(): + if field in field_skip: + continue + + mapping = field_mapping.get(field) + f = field + if mapping is not None: + field = mapping[0] if mapping[0] else field + f = mapping[1] if mapping[1] else field + + p("!{}".format(field)) + p("|[[{}::{}]]".format(f, value)) + p("|-") + p("|}") + + p() + p("[[Category:Generated]]") + p("[[Category:FPGA Chip]]") + p("[[Category:Artix-7 generated data set]]") diff --git a/Artix-7/temperatures.csv b/Artix-7/temperatures.csv new file mode 100644 index 0000000..074c093 --- /dev/null +++ b/Artix-7/temperatures.csv @@ -0,0 +1,5 @@ +code,name,min,max +C,Commercial Temp (C),0,85 +E,Extended Temp (E),0,100 +I,Industrial Temp (I),-40,100 +Q,Expanded (Q) ,-40,125 diff --git a/docs/ds180_7Series_Overview.pdf b/docs/ds180_7Series_Overview.pdf new file mode 100644 index 0000000..43110cb Binary files /dev/null and b/docs/ds180_7Series_Overview.pdf differ -- cgit v1.2.3