From abb3a34a0557733a7c3754291ea689e44f9a9689 Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Wed, 15 Aug 2018 13:55:44 +0200 Subject: o Adding pages for Kintex-7. --- Artix-7/mw.j2 | 2 +- Artix-7/mw/Chip:XC7A100T.mw | 2 +- Artix-7/mw/Chip:XC7A12T.mw | 2 +- Artix-7/mw/Chip:XC7A15T.mw | 2 +- Artix-7/mw/Chip:XC7A200T.mw | 2 +- Artix-7/mw/Chip:XC7A25T.mw | 2 +- Artix-7/mw/Chip:XC7A35T.mw | 2 +- Artix-7/mw/Chip:XC7A50T.mw | 2 +- Artix-7/mw/Chip:XC7A75T.mw | 2 +- Kintex-7/mw.j2 | 4 ++-- Kintex-7/mw/Chip:XC7K160T.mw | 4 ++-- Kintex-7/mw/Chip:XC7K325T.mw | 4 ++-- Kintex-7/mw/Chip:XC7K355T.mw | 4 ++-- Kintex-7/mw/Chip:XC7K410T.mw | 4 ++-- Kintex-7/mw/Chip:XC7K420T.mw | 4 ++-- Kintex-7/mw/Chip:XC7K480T.mw | 4 ++-- Kintex-7/mw/Chip:XC7K70T.mw | 4 ++-- 17 files changed, 25 insertions(+), 25 deletions(-) diff --git a/Artix-7/mw.j2 b/Artix-7/mw.j2 index 6a0cb90..2b7c418 100644 --- a/Artix-7/mw.j2 +++ b/Artix-7/mw.j2 @@ -38,8 +38,8 @@ * [[Has hard core::Gigabit transceiver;{{ part["GTPs"] }}]] {% endif %} {% if part["PCIe"] %} -* [[Has hard core::PCIe;{{ part["PCIe"] }}]] * [[Has hard core::PCIe Gen 2;{{ part["PCIe"] }}]] +{{ "{{" }}#set: Has hard core=PCIe;{{ part["PCIe"] }} }} {% endif %} {% if part["XADC Blocks"] %} * [[Has hard core::XADC;{{ part["XADC Blocks"] }}]] diff --git a/Artix-7/mw/Chip:XC7A100T.mw b/Artix-7/mw/Chip:XC7A100T.mw index 078246e..a0fc091 100644 --- a/Artix-7/mw/Chip:XC7A100T.mw +++ b/Artix-7/mw/Chip:XC7A100T.mw @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;8]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} * [[Has hard core::XADC;1]] * [[Has hard core::DSP48E1 slice;240]] diff --git a/Artix-7/mw/Chip:XC7A12T.mw b/Artix-7/mw/Chip:XC7A12T.mw index 2ac72ac..90ae0e9 100644 --- a/Artix-7/mw/Chip:XC7A12T.mw +++ b/Artix-7/mw/Chip:XC7A12T.mw @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;2]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} * [[Has hard core::XADC;1]] * [[Has hard core::DSP48E1 slice;40]] diff --git a/Artix-7/mw/Chip:XC7A15T.mw b/Artix-7/mw/Chip:XC7A15T.mw index 82d7e18..da7f216 100644 --- a/Artix-7/mw/Chip:XC7A15T.mw +++ b/Artix-7/mw/Chip:XC7A15T.mw @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;4]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} * [[Has hard core::XADC;1]] * [[Has hard core::DSP48E1 slice;45]] diff --git a/Artix-7/mw/Chip:XC7A200T.mw b/Artix-7/mw/Chip:XC7A200T.mw index 293e07e..f86b49d 100644 --- a/Artix-7/mw/Chip:XC7A200T.mw +++ b/Artix-7/mw/Chip:XC7A200T.mw @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;16]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} * [[Has hard core::XADC;1]] * [[Has hard core::DSP48E1 slice;740]] diff --git a/Artix-7/mw/Chip:XC7A25T.mw b/Artix-7/mw/Chip:XC7A25T.mw index e60ea9d..3b898da 100644 --- a/Artix-7/mw/Chip:XC7A25T.mw +++ b/Artix-7/mw/Chip:XC7A25T.mw @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;4]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} * [[Has hard core::XADC;1]] * [[Has hard core::DSP48E1 slice;80]] diff --git a/Artix-7/mw/Chip:XC7A35T.mw b/Artix-7/mw/Chip:XC7A35T.mw index f04f0a2..ca5238d 100644 --- a/Artix-7/mw/Chip:XC7A35T.mw +++ b/Artix-7/mw/Chip:XC7A35T.mw @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;4]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} * [[Has hard core::XADC;1]] * [[Has hard core::DSP48E1 slice;90]] diff --git a/Artix-7/mw/Chip:XC7A50T.mw b/Artix-7/mw/Chip:XC7A50T.mw index 45469ab..1c48103 100644 --- a/Artix-7/mw/Chip:XC7A50T.mw +++ b/Artix-7/mw/Chip:XC7A50T.mw @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;4]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} * [[Has hard core::XADC;1]] * [[Has hard core::DSP48E1 slice;120]] diff --git a/Artix-7/mw/Chip:XC7A75T.mw b/Artix-7/mw/Chip:XC7A75T.mw index 6f943bc..fbee874 100644 --- a/Artix-7/mw/Chip:XC7A75T.mw +++ b/Artix-7/mw/Chip:XC7A75T.mw @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;8]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} * [[Has hard core::XADC;1]] * [[Has hard core::DSP48E1 slice;180]] diff --git a/Kintex-7/mw.j2 b/Kintex-7/mw.j2 index 01f80ef..482c501 100644 --- a/Kintex-7/mw.j2 +++ b/Kintex-7/mw.j2 @@ -1,6 +1,6 @@ = Overview = -[[Part number::{{ part["Part number"] }}]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. +[[Part number::{{ part["Device"] }}]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. {|class='wikitable' !Logic Cells @@ -38,8 +38,8 @@ * [[Has hard core::Gigabit transceiver;{{ part["GTXs"] }}]] {% endif %} {% if part["PCIe"] %} -* [[Has hard core::PCIe;{{ part["PCIe"] }}]] * [[Has hard core::PCIe Gen 2;{{ part["PCIe"] }}]] +{{ "{{" }}#set: Has hard core=PCIe;{{ part["PCIe"] }} }} {% endif %} {% if part["XADC Blocks"] %} * [[Has hard core::XADC;{{ part["XADC Blocks"] }}]] diff --git a/Kintex-7/mw/Chip:XC7K160T.mw b/Kintex-7/mw/Chip:XC7K160T.mw index 0698263..161c391 100644 --- a/Kintex-7/mw/Chip:XC7K160T.mw +++ b/Kintex-7/mw/Chip:XC7K160T.mw @@ -1,6 +1,6 @@ = Overview = -[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. +[[Part number::XC7K160T]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. {|class='wikitable' !Logic Cells @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;8]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} [[Category:Generated]] [[Category:Xilinx Kintex-7 family chip|Kintex-7]] diff --git a/Kintex-7/mw/Chip:XC7K325T.mw b/Kintex-7/mw/Chip:XC7K325T.mw index bcd44c6..8b05fc1 100644 --- a/Kintex-7/mw/Chip:XC7K325T.mw +++ b/Kintex-7/mw/Chip:XC7K325T.mw @@ -1,6 +1,6 @@ = Overview = -[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. +[[Part number::XC7K325T]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. {|class='wikitable' !Logic Cells @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;16]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} [[Category:Generated]] [[Category:Xilinx Kintex-7 family chip|Kintex-7]] diff --git a/Kintex-7/mw/Chip:XC7K355T.mw b/Kintex-7/mw/Chip:XC7K355T.mw index 1043a31..65f7e36 100644 --- a/Kintex-7/mw/Chip:XC7K355T.mw +++ b/Kintex-7/mw/Chip:XC7K355T.mw @@ -1,6 +1,6 @@ = Overview = -[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. +[[Part number::XC7K355T]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. {|class='wikitable' !Logic Cells @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;24]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} [[Category:Generated]] [[Category:Xilinx Kintex-7 family chip|Kintex-7]] diff --git a/Kintex-7/mw/Chip:XC7K410T.mw b/Kintex-7/mw/Chip:XC7K410T.mw index 733e056..1f078ee 100644 --- a/Kintex-7/mw/Chip:XC7K410T.mw +++ b/Kintex-7/mw/Chip:XC7K410T.mw @@ -1,6 +1,6 @@ = Overview = -[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. +[[Part number::XC7K410T]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. {|class='wikitable' !Logic Cells @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;16]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} [[Category:Generated]] [[Category:Xilinx Kintex-7 family chip|Kintex-7]] diff --git a/Kintex-7/mw/Chip:XC7K420T.mw b/Kintex-7/mw/Chip:XC7K420T.mw index dc59e81..ba13bd4 100644 --- a/Kintex-7/mw/Chip:XC7K420T.mw +++ b/Kintex-7/mw/Chip:XC7K420T.mw @@ -1,6 +1,6 @@ = Overview = -[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. +[[Part number::XC7K420T]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. {|class='wikitable' !Logic Cells @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;32]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} [[Category:Generated]] [[Category:Xilinx Kintex-7 family chip|Kintex-7]] diff --git a/Kintex-7/mw/Chip:XC7K480T.mw b/Kintex-7/mw/Chip:XC7K480T.mw index b5a1bf3..632bd54 100644 --- a/Kintex-7/mw/Chip:XC7K480T.mw +++ b/Kintex-7/mw/Chip:XC7K480T.mw @@ -1,6 +1,6 @@ = Overview = -[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. +[[Part number::XC7K480T]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. {|class='wikitable' !Logic Cells @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;32]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} [[Category:Generated]] [[Category:Xilinx Kintex-7 family chip|Kintex-7]] diff --git a/Kintex-7/mw/Chip:XC7K70T.mw b/Kintex-7/mw/Chip:XC7K70T.mw index 206e1bc..6f79905 100644 --- a/Kintex-7/mw/Chip:XC7K70T.mw +++ b/Kintex-7/mw/Chip:XC7K70T.mw @@ -1,6 +1,6 @@ = Overview = -[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. +[[Part number::XC7K70T]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]]. {|class='wikitable' !Logic Cells @@ -35,8 +35,8 @@ = Hard cores = * [[Has hard core::Gigabit transceiver;8]] -* [[Has hard core::PCIe;1]] * [[Has hard core::PCIe Gen 2;1]] +{{#set: Has hard core=PCIe;1 }} [[Category:Generated]] [[Category:Xilinx Kintex-7 family chip|Kintex-7]] -- cgit v1.2.3