From efb5d278f0089be5ae9a5083e92684ee922b5c2e Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Mon, 13 Aug 2018 23:41:30 +0200 Subject: o Generating under the Chip namespace. --- Artix-7/mw/Chip:XC7A100T.mw | 46 +++++++++++++++++++++++++++++++++++++++++++++ Artix-7/mw/Chip:XC7A12T.mw | 46 +++++++++++++++++++++++++++++++++++++++++++++ Artix-7/mw/Chip:XC7A15T.mw | 46 +++++++++++++++++++++++++++++++++++++++++++++ Artix-7/mw/Chip:XC7A200T.mw | 46 +++++++++++++++++++++++++++++++++++++++++++++ Artix-7/mw/Chip:XC7A25T.mw | 46 +++++++++++++++++++++++++++++++++++++++++++++ Artix-7/mw/Chip:XC7A35T.mw | 46 +++++++++++++++++++++++++++++++++++++++++++++ Artix-7/mw/Chip:XC7A50T.mw | 46 +++++++++++++++++++++++++++++++++++++++++++++ Artix-7/mw/Chip:XC7A75T.mw | 46 +++++++++++++++++++++++++++++++++++++++++++++ Artix-7/mw/XC7A100T.mw | 46 --------------------------------------------- Artix-7/mw/XC7A12T.mw | 46 --------------------------------------------- Artix-7/mw/XC7A15T.mw | 46 --------------------------------------------- Artix-7/mw/XC7A200T.mw | 46 --------------------------------------------- Artix-7/mw/XC7A25T.mw | 46 --------------------------------------------- Artix-7/mw/XC7A35T.mw | 46 --------------------------------------------- Artix-7/mw/XC7A50T.mw | 46 --------------------------------------------- Artix-7/mw/XC7A75T.mw | 46 --------------------------------------------- Artix-7/run.py | 2 +- 17 files changed, 369 insertions(+), 369 deletions(-) create mode 100644 Artix-7/mw/Chip:XC7A100T.mw create mode 100644 Artix-7/mw/Chip:XC7A12T.mw create mode 100644 Artix-7/mw/Chip:XC7A15T.mw create mode 100644 Artix-7/mw/Chip:XC7A200T.mw create mode 100644 Artix-7/mw/Chip:XC7A25T.mw create mode 100644 Artix-7/mw/Chip:XC7A35T.mw create mode 100644 Artix-7/mw/Chip:XC7A50T.mw create mode 100644 Artix-7/mw/Chip:XC7A75T.mw delete mode 100644 Artix-7/mw/XC7A100T.mw delete mode 100644 Artix-7/mw/XC7A12T.mw delete mode 100644 Artix-7/mw/XC7A15T.mw delete mode 100644 Artix-7/mw/XC7A200T.mw delete mode 100644 Artix-7/mw/XC7A25T.mw delete mode 100644 Artix-7/mw/XC7A35T.mw delete mode 100644 Artix-7/mw/XC7A50T.mw delete mode 100644 Artix-7/mw/XC7A75T.mw diff --git a/Artix-7/mw/Chip:XC7A100T.mw b/Artix-7/mw/Chip:XC7A100T.mw new file mode 100644 index 0000000..593238a --- /dev/null +++ b/Artix-7/mw/Chip:XC7A100T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A100T]] +|- +!Logic Cells +|[[Xilix logic cells::101440]] +|- +!Slices +|[[Xilix 7 series slices::15850]] +|- +!Distributed RAM +|[[Distributed RAM::1188 kB]] +|- +!RAM blocks +|[[RAM blocks::135]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::4860 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::6]] +|- +!Available IO +|[[Available IO::300]] +|- +!IO banks +|[[IO banks::6]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;8]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;240]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/Chip:XC7A12T.mw b/Artix-7/mw/Chip:XC7A12T.mw new file mode 100644 index 0000000..df498b8 --- /dev/null +++ b/Artix-7/mw/Chip:XC7A12T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A12T]] +|- +!Logic Cells +|[[Xilix logic cells::12800]] +|- +!Slices +|[[Xilix 7 series slices::2000]] +|- +!Distributed RAM +|[[Distributed RAM::171 kB]] +|- +!RAM blocks +|[[RAM blocks::20]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::720 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::3]] +|- +!Available IO +|[[Available IO::150]] +|- +!IO banks +|[[IO banks::3]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;2]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;40]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/Chip:XC7A15T.mw b/Artix-7/mw/Chip:XC7A15T.mw new file mode 100644 index 0000000..b7900a6 --- /dev/null +++ b/Artix-7/mw/Chip:XC7A15T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A15T]] +|- +!Logic Cells +|[[Xilix logic cells::16640]] +|- +!Slices +|[[Xilix 7 series slices::2600]] +|- +!Distributed RAM +|[[Distributed RAM::200 kB]] +|- +!RAM blocks +|[[RAM blocks::25]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::900 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::5]] +|- +!Available IO +|[[Available IO::250]] +|- +!IO banks +|[[IO banks::5]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;4]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;45]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/Chip:XC7A200T.mw b/Artix-7/mw/Chip:XC7A200T.mw new file mode 100644 index 0000000..bfa2f66 --- /dev/null +++ b/Artix-7/mw/Chip:XC7A200T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A200T]] +|- +!Logic Cells +|[[Xilix logic cells::215360]] +|- +!Slices +|[[Xilix 7 series slices::33650]] +|- +!Distributed RAM +|[[Distributed RAM::2888 kB]] +|- +!RAM blocks +|[[RAM blocks::365]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::13140 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::10]] +|- +!Available IO +|[[Available IO::500]] +|- +!IO banks +|[[IO banks::10]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;16]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;740]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/Chip:XC7A25T.mw b/Artix-7/mw/Chip:XC7A25T.mw new file mode 100644 index 0000000..266d05a --- /dev/null +++ b/Artix-7/mw/Chip:XC7A25T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A25T]] +|- +!Logic Cells +|[[Xilix logic cells::23360]] +|- +!Slices +|[[Xilix 7 series slices::3650]] +|- +!Distributed RAM +|[[Distributed RAM::313 kB]] +|- +!RAM blocks +|[[RAM blocks::45]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::1620 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::3]] +|- +!Available IO +|[[Available IO::150]] +|- +!IO banks +|[[IO banks::3]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;4]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;80]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/Chip:XC7A35T.mw b/Artix-7/mw/Chip:XC7A35T.mw new file mode 100644 index 0000000..93d8bba --- /dev/null +++ b/Artix-7/mw/Chip:XC7A35T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A35T]] +|- +!Logic Cells +|[[Xilix logic cells::33280]] +|- +!Slices +|[[Xilix 7 series slices::5200]] +|- +!Distributed RAM +|[[Distributed RAM::400 kB]] +|- +!RAM blocks +|[[RAM blocks::50]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::1800 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::5]] +|- +!Available IO +|[[Available IO::250]] +|- +!IO banks +|[[IO banks::5]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;4]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;90]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/Chip:XC7A50T.mw b/Artix-7/mw/Chip:XC7A50T.mw new file mode 100644 index 0000000..106769f --- /dev/null +++ b/Artix-7/mw/Chip:XC7A50T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A50T]] +|- +!Logic Cells +|[[Xilix logic cells::52160]] +|- +!Slices +|[[Xilix 7 series slices::8150]] +|- +!Distributed RAM +|[[Distributed RAM::600 kB]] +|- +!RAM blocks +|[[RAM blocks::75]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::2700 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::5]] +|- +!Available IO +|[[Available IO::250]] +|- +!IO banks +|[[IO banks::5]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;4]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;120]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/Chip:XC7A75T.mw b/Artix-7/mw/Chip:XC7A75T.mw new file mode 100644 index 0000000..02d5890 --- /dev/null +++ b/Artix-7/mw/Chip:XC7A75T.mw @@ -0,0 +1,46 @@ += Overview = + +{|class='wikitable' +!Part number +|[[Part number::XC7A75T]] +|- +!Logic Cells +|[[Xilix logic cells::75520]] +|- +!Slices +|[[Xilix 7 series slices::11800]] +|- +!Distributed RAM +|[[Distributed RAM::892 kB]] +|- +!RAM blocks +|[[RAM blocks::105]] +|- +!RAM block size +|[[RAM block size::36 kB]] +|- +!Total RAM +|[[RAM::3780 kB]] +|- +!Clock management tiles +|[[Xilix clock management tiles::6]] +|- +!Available IO +|[[Available IO::300]] +|- +!IO banks +|[[IO banks::6]] +|- +|} + += Hard cores = + +* [[Has hard core::Gigabit transceiver;8]] +* [[Has hard core::PCIe;1]] +* [[Has hard core::PCIe Gen 2;1]] +* [[Has hard core::XADC;1]] +* [[Has hard core::DSP48E1 slice;180]] + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A100T.mw b/Artix-7/mw/XC7A100T.mw deleted file mode 100644 index 593238a..0000000 --- a/Artix-7/mw/XC7A100T.mw +++ /dev/null @@ -1,46 +0,0 @@ -= Overview = - -{|class='wikitable' -!Part number -|[[Part number::XC7A100T]] -|- -!Logic Cells -|[[Xilix logic cells::101440]] -|- -!Slices -|[[Xilix 7 series slices::15850]] -|- -!Distributed RAM -|[[Distributed RAM::1188 kB]] -|- -!RAM blocks -|[[RAM blocks::135]] -|- -!RAM block size -|[[RAM block size::36 kB]] -|- -!Total RAM -|[[RAM::4860 kB]] -|- -!Clock management tiles -|[[Xilix clock management tiles::6]] -|- -!Available IO -|[[Available IO::300]] -|- -!IO banks -|[[IO banks::6]] -|- -|} - -= Hard cores = - -* [[Has hard core::Gigabit transceiver;8]] -* [[Has hard core::PCIe;1]] -* [[Has hard core::PCIe Gen 2;1]] -* [[Has hard core::XADC;1]] -* [[Has hard core::DSP48E1 slice;240]] - -[[Category:Generated]] -[[Category:FPGA Chip]] -[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw deleted file mode 100644 index df498b8..0000000 --- a/Artix-7/mw/XC7A12T.mw +++ /dev/null @@ -1,46 +0,0 @@ -= Overview = - -{|class='wikitable' -!Part number -|[[Part number::XC7A12T]] -|- -!Logic Cells -|[[Xilix logic cells::12800]] -|- -!Slices -|[[Xilix 7 series slices::2000]] -|- -!Distributed RAM -|[[Distributed RAM::171 kB]] -|- -!RAM blocks -|[[RAM blocks::20]] -|- -!RAM block size -|[[RAM block size::36 kB]] -|- -!Total RAM -|[[RAM::720 kB]] -|- -!Clock management tiles -|[[Xilix clock management tiles::3]] -|- -!Available IO -|[[Available IO::150]] -|- -!IO banks -|[[IO banks::3]] -|- -|} - -= Hard cores = - -* [[Has hard core::Gigabit transceiver;2]] -* [[Has hard core::PCIe;1]] -* [[Has hard core::PCIe Gen 2;1]] -* [[Has hard core::XADC;1]] -* [[Has hard core::DSP48E1 slice;40]] - -[[Category:Generated]] -[[Category:FPGA Chip]] -[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A15T.mw b/Artix-7/mw/XC7A15T.mw deleted file mode 100644 index b7900a6..0000000 --- a/Artix-7/mw/XC7A15T.mw +++ /dev/null @@ -1,46 +0,0 @@ -= Overview = - -{|class='wikitable' -!Part number -|[[Part number::XC7A15T]] -|- -!Logic Cells -|[[Xilix logic cells::16640]] -|- -!Slices -|[[Xilix 7 series slices::2600]] -|- -!Distributed RAM -|[[Distributed RAM::200 kB]] -|- -!RAM blocks -|[[RAM blocks::25]] -|- -!RAM block size -|[[RAM block size::36 kB]] -|- -!Total RAM -|[[RAM::900 kB]] -|- -!Clock management tiles -|[[Xilix clock management tiles::5]] -|- -!Available IO -|[[Available IO::250]] -|- -!IO banks -|[[IO banks::5]] -|- -|} - -= Hard cores = - -* [[Has hard core::Gigabit transceiver;4]] -* [[Has hard core::PCIe;1]] -* [[Has hard core::PCIe Gen 2;1]] -* [[Has hard core::XADC;1]] -* [[Has hard core::DSP48E1 slice;45]] - -[[Category:Generated]] -[[Category:FPGA Chip]] -[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A200T.mw b/Artix-7/mw/XC7A200T.mw deleted file mode 100644 index bfa2f66..0000000 --- a/Artix-7/mw/XC7A200T.mw +++ /dev/null @@ -1,46 +0,0 @@ -= Overview = - -{|class='wikitable' -!Part number -|[[Part number::XC7A200T]] -|- -!Logic Cells -|[[Xilix logic cells::215360]] -|- -!Slices -|[[Xilix 7 series slices::33650]] -|- -!Distributed RAM -|[[Distributed RAM::2888 kB]] -|- -!RAM blocks -|[[RAM blocks::365]] -|- -!RAM block size -|[[RAM block size::36 kB]] -|- -!Total RAM -|[[RAM::13140 kB]] -|- -!Clock management tiles -|[[Xilix clock management tiles::10]] -|- -!Available IO -|[[Available IO::500]] -|- -!IO banks -|[[IO banks::10]] -|- -|} - -= Hard cores = - -* [[Has hard core::Gigabit transceiver;16]] -* [[Has hard core::PCIe;1]] -* [[Has hard core::PCIe Gen 2;1]] -* [[Has hard core::XADC;1]] -* [[Has hard core::DSP48E1 slice;740]] - -[[Category:Generated]] -[[Category:FPGA Chip]] -[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A25T.mw b/Artix-7/mw/XC7A25T.mw deleted file mode 100644 index 266d05a..0000000 --- a/Artix-7/mw/XC7A25T.mw +++ /dev/null @@ -1,46 +0,0 @@ -= Overview = - -{|class='wikitable' -!Part number -|[[Part number::XC7A25T]] -|- -!Logic Cells -|[[Xilix logic cells::23360]] -|- -!Slices -|[[Xilix 7 series slices::3650]] -|- -!Distributed RAM -|[[Distributed RAM::313 kB]] -|- -!RAM blocks -|[[RAM blocks::45]] -|- -!RAM block size -|[[RAM block size::36 kB]] -|- -!Total RAM -|[[RAM::1620 kB]] -|- -!Clock management tiles -|[[Xilix clock management tiles::3]] -|- -!Available IO -|[[Available IO::150]] -|- -!IO banks -|[[IO banks::3]] -|- -|} - -= Hard cores = - -* [[Has hard core::Gigabit transceiver;4]] -* [[Has hard core::PCIe;1]] -* [[Has hard core::PCIe Gen 2;1]] -* [[Has hard core::XADC;1]] -* [[Has hard core::DSP48E1 slice;80]] - -[[Category:Generated]] -[[Category:FPGA Chip]] -[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A35T.mw b/Artix-7/mw/XC7A35T.mw deleted file mode 100644 index 93d8bba..0000000 --- a/Artix-7/mw/XC7A35T.mw +++ /dev/null @@ -1,46 +0,0 @@ -= Overview = - -{|class='wikitable' -!Part number -|[[Part number::XC7A35T]] -|- -!Logic Cells -|[[Xilix logic cells::33280]] -|- -!Slices -|[[Xilix 7 series slices::5200]] -|- -!Distributed RAM -|[[Distributed RAM::400 kB]] -|- -!RAM blocks -|[[RAM blocks::50]] -|- -!RAM block size -|[[RAM block size::36 kB]] -|- -!Total RAM -|[[RAM::1800 kB]] -|- -!Clock management tiles -|[[Xilix clock management tiles::5]] -|- -!Available IO -|[[Available IO::250]] -|- -!IO banks -|[[IO banks::5]] -|- -|} - -= Hard cores = - -* [[Has hard core::Gigabit transceiver;4]] -* [[Has hard core::PCIe;1]] -* [[Has hard core::PCIe Gen 2;1]] -* [[Has hard core::XADC;1]] -* [[Has hard core::DSP48E1 slice;90]] - -[[Category:Generated]] -[[Category:FPGA Chip]] -[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A50T.mw b/Artix-7/mw/XC7A50T.mw deleted file mode 100644 index 106769f..0000000 --- a/Artix-7/mw/XC7A50T.mw +++ /dev/null @@ -1,46 +0,0 @@ -= Overview = - -{|class='wikitable' -!Part number -|[[Part number::XC7A50T]] -|- -!Logic Cells -|[[Xilix logic cells::52160]] -|- -!Slices -|[[Xilix 7 series slices::8150]] -|- -!Distributed RAM -|[[Distributed RAM::600 kB]] -|- -!RAM blocks -|[[RAM blocks::75]] -|- -!RAM block size -|[[RAM block size::36 kB]] -|- -!Total RAM -|[[RAM::2700 kB]] -|- -!Clock management tiles -|[[Xilix clock management tiles::5]] -|- -!Available IO -|[[Available IO::250]] -|- -!IO banks -|[[IO banks::5]] -|- -|} - -= Hard cores = - -* [[Has hard core::Gigabit transceiver;4]] -* [[Has hard core::PCIe;1]] -* [[Has hard core::PCIe Gen 2;1]] -* [[Has hard core::XADC;1]] -* [[Has hard core::DSP48E1 slice;120]] - -[[Category:Generated]] -[[Category:FPGA Chip]] -[[Category:Artix-7 generated data set]] diff --git a/Artix-7/mw/XC7A75T.mw b/Artix-7/mw/XC7A75T.mw deleted file mode 100644 index 02d5890..0000000 --- a/Artix-7/mw/XC7A75T.mw +++ /dev/null @@ -1,46 +0,0 @@ -= Overview = - -{|class='wikitable' -!Part number -|[[Part number::XC7A75T]] -|- -!Logic Cells -|[[Xilix logic cells::75520]] -|- -!Slices -|[[Xilix 7 series slices::11800]] -|- -!Distributed RAM -|[[Distributed RAM::892 kB]] -|- -!RAM blocks -|[[RAM blocks::105]] -|- -!RAM block size -|[[RAM block size::36 kB]] -|- -!Total RAM -|[[RAM::3780 kB]] -|- -!Clock management tiles -|[[Xilix clock management tiles::6]] -|- -!Available IO -|[[Available IO::300]] -|- -!IO banks -|[[IO banks::6]] -|- -|} - -= Hard cores = - -* [[Has hard core::Gigabit transceiver;8]] -* [[Has hard core::PCIe;1]] -* [[Has hard core::PCIe Gen 2;1]] -* [[Has hard core::XADC;1]] -* [[Has hard core::DSP48E1 slice;180]] - -[[Category:Generated]] -[[Category:FPGA Chip]] -[[Category:Artix-7 generated data set]] diff --git a/Artix-7/run.py b/Artix-7/run.py index f8caf8f..c841adf 100755 --- a/Artix-7/run.py +++ b/Artix-7/run.py @@ -124,7 +124,7 @@ with open("parts.csv") as f: part_number = part["Part number"] print("--- PART: {} ---".format(part_number)) - path = out_dir / "{}.mw".format(part_number) + path = out_dir / "Chip:{}.mw".format(part_number) with open(path, "w") as out: template = env.get_template("mw.j2") out.write(template.render(part=part)) -- cgit v1.2.3