From efb5d278f0089be5ae9a5083e92684ee922b5c2e Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Mon, 13 Aug 2018 23:41:30 +0200
Subject: o Generating under the Chip namespace.

---
 Artix-7/mw/Chip:XC7A12T.mw | 46 ++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)
 create mode 100644 Artix-7/mw/Chip:XC7A12T.mw

(limited to 'Artix-7/mw/Chip:XC7A12T.mw')

diff --git a/Artix-7/mw/Chip:XC7A12T.mw b/Artix-7/mw/Chip:XC7A12T.mw
new file mode 100644
index 0000000..df498b8
--- /dev/null
+++ b/Artix-7/mw/Chip:XC7A12T.mw
@@ -0,0 +1,46 @@
+= Overview =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A12T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::12800]]
+|-
+!Slices
+|[[Xilix 7 series slices::2000]]
+|-
+!Distributed RAM
+|[[Distributed RAM::171 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::20]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::720 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::3]]
+|-
+!Available IO
+|[[Available IO::150]]
+|-
+!IO banks
+|[[IO banks::3]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;2]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;40]]
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
-- 
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