From 07a64e370e06603c9702e93e6b54540b320c2cda Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Mon, 13 Aug 2018 20:46:09 +0200
Subject: o Generating mediawiki pages from Artix-7 docs.

---
 Artix-7/mw/XC7A12T.mw | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 53 insertions(+)
 create mode 100644 Artix-7/mw/XC7A12T.mw

(limited to 'Artix-7/mw/XC7A12T.mw')

diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw
new file mode 100644
index 0000000..7d37600
--- /dev/null
+++ b/Artix-7/mw/XC7A12T.mw
@@ -0,0 +1,53 @@
+= XC7A12T =
+
+{|class='wikitable'
+!Part number
+|[[Part number::XC7A12T]]
+|-
+!Logic Cells
+|[[Xilix logic cells::12800]]
+|-
+!Slices
+|[[Slices::2000]]
+|-
+!Max Distributed RAM
+|[[Max Distributed RAM::171]]
+|-
+!DSP48E1 Slices
+|[[DSP48E1 Slices::40]]
+|-
+!18 Kb
+|[[18 Kb::40]]
+|-
+!RAM blocks
+|[[RAM blocks::20]]
+|-
+!Max
+|[[Max::720]]
+|-
+!Clock management tiles
+|[[Xilix Clock management tiles::3]]
+|-
+!PCIe
+|[[PCIe::1]]
+|-
+!GTPs
+|[[GTPs::2]]
+|-
+!XADC Blocks
+|[[XADC Blocks::1]]
+|-
+!IO banks
+|[[IO banks::3]]
+|-
+!Max User I/O
+|[[Max User I/O::150]]
+|-
+!RAM Block Size
+|[[RAM Block Size::36 kB]]
+|-
+|}
+
+[[Category:Generated]]
+[[Category:FPGA Chip]]
+[[Category:Artix-7 generated data set]]
-- 
cgit v1.2.3