From 77af3b8b331d4a67a3523f03081b1e2a98915a0a Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Mon, 13 Aug 2018 23:20:28 +0200
Subject: o Using 'Has hard core' record property for a few values.

---
 Artix-7/mw/XC7A12T.mw | 34 ++++++++++++++++------------------
 1 file changed, 16 insertions(+), 18 deletions(-)

(limited to 'Artix-7/mw/XC7A12T.mw')

diff --git a/Artix-7/mw/XC7A12T.mw b/Artix-7/mw/XC7A12T.mw
index 726ccf7..30e4757 100644
--- a/Artix-7/mw/XC7A12T.mw
+++ b/Artix-7/mw/XC7A12T.mw
@@ -1,5 +1,7 @@
 = XC7A12T =
 
+== Overview ==
+
 {|class='wikitable'
 !Part number
 |[[Part number::XC7A12T]]
@@ -13,38 +15,34 @@
 !Distributed RAM
 |[[Distributed RAM::171 kB]]
 |-
-!DSP48E1 Slices
-|[[DSP48E1 Slices::40]]
-|-
 !RAM blocks
 |[[RAM blocks::20]]
 |-
-!RAM
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
 |[[RAM::720 kB]]
 |-
 !Clock management tiles
 |[[Xilix clock management tiles::3]]
 |-
-!PCIe
-|[[PCIe::1]]
-|-
-!GTPs
-|[[GTPs::2]]
-|-
-!XADC Blocks
-|[[XADC Blocks::1]]
-|-
-!IO banks
-|[[IO banks::3]]
-|-
 !Available IO
 |[[Available IO::150]]
 |-
-!RAM block size
-|[[RAM block size::36 kB]]
+!IO banks
+|[[IO banks::3]]
 |-
 |}
 
+== Hard cores ==
+
+* [[Has hard core::Gigabit transceiver;2]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+* [[Has hard core::XADC;1]]
+* [[Has hard core::DSP48E1 slice;40]]
+
 [[Category:Generated]]
 [[Category:FPGA Chip]]
 [[Category:Artix-7 generated data set]]
-- 
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