From 07a64e370e06603c9702e93e6b54540b320c2cda Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Mon, 13 Aug 2018 20:46:09 +0200 Subject: o Generating mediawiki pages from Artix-7 docs. --- Artix-7/mw/XC7A75T.mw | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Artix-7/mw/XC7A75T.mw (limited to 'Artix-7/mw/XC7A75T.mw') diff --git a/Artix-7/mw/XC7A75T.mw b/Artix-7/mw/XC7A75T.mw new file mode 100644 index 0000000..6ca4f2f --- /dev/null +++ b/Artix-7/mw/XC7A75T.mw @@ -0,0 +1,53 @@ += XC7A75T = + +{|class='wikitable' +!Part number +|[[Part number::XC7A75T]] +|- +!Logic Cells +|[[Xilix logic cells::75520]] +|- +!Slices +|[[Slices::11800]] +|- +!Max Distributed RAM +|[[Max Distributed RAM::892]] +|- +!DSP48E1 Slices +|[[DSP48E1 Slices::180]] +|- +!18 Kb +|[[18 Kb::210]] +|- +!RAM blocks +|[[RAM blocks::105]] +|- +!Max +|[[Max::3780]] +|- +!Clock management tiles +|[[Xilix Clock management tiles::6]] +|- +!PCIe +|[[PCIe::1]] +|- +!GTPs +|[[GTPs::8]] +|- +!XADC Blocks +|[[XADC Blocks::1]] +|- +!IO banks +|[[IO banks::6]] +|- +!Max User I/O +|[[Max User I/O::300]] +|- +!RAM Block Size +|[[RAM Block Size::36 kB]] +|- +|} + +[[Category:Generated]] +[[Category:FPGA Chip]] +[[Category:Artix-7 generated data set]] -- cgit v1.2.3