From 5b53ca0700189ebb98278a8081bdabf527f1bb12 Mon Sep 17 00:00:00 2001
From: Trygve Laugstøl <trygvis@inamo.no>
Date: Wed, 15 Aug 2018 13:47:39 +0200
Subject: o Kintex-7.

---
 Kintex-7/mw/Chip:XC7K480T.mw | 43 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 Kintex-7/mw/Chip:XC7K480T.mw

(limited to 'Kintex-7/mw/Chip:XC7K480T.mw')

diff --git a/Kintex-7/mw/Chip:XC7K480T.mw b/Kintex-7/mw/Chip:XC7K480T.mw
new file mode 100644
index 0000000..b5a1bf3
--- /dev/null
+++ b/Kintex-7/mw/Chip:XC7K480T.mw
@@ -0,0 +1,43 @@
+= Overview =
+
+[[Part number::]] is an FPGA in the [[Chip family::Kintex-7]] family from [[Manufacturer::Xilinx]].
+
+{|class='wikitable'
+!Logic Cells
+|[[Xilix logic cells::477760]]
+|-
+!Slices
+|[[Xilix 7 series slices::74650]]
+|-
+!Distributed RAM
+|[[Distributed RAM::6788 kB]]
+|-
+!RAM blocks
+|[[RAM blocks::955]]
+|-
+!RAM block size
+|[[RAM block size::36 kB]]
+|-
+!Total RAM
+|[[RAM::34380 kB]]
+|-
+!Clock management tiles
+|[[Xilix clock management tiles::8]]
+|-
+!Available IO
+|[[Available IO::400]]
+|-
+!IO banks
+|[[IO banks::8]]
+|-
+|}
+
+= Hard cores =
+
+* [[Has hard core::Gigabit transceiver;32]]
+* [[Has hard core::PCIe;1]]
+* [[Has hard core::PCIe Gen 2;1]]
+
+[[Category:Generated]]
+[[Category:Xilinx Kintex-7 family chip|Kintex-7]]
+[[Category:Kintex-7 generated data set]]
-- 
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