From ec429f152cf1d32a86f5783ed87453b42f7ef190 Mon Sep 17 00:00:00 2001 From: Trygve Laugstøl Date: Mon, 20 Aug 2018 23:28:00 +0200 Subject: o Better STM32 setup. --- stm32/run.py | 76 ++++++++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 56 insertions(+), 20 deletions(-) (limited to 'stm32/run.py') diff --git a/stm32/run.py b/stm32/run.py index 097dbd2..521372c 100755 --- a/stm32/run.py +++ b/stm32/run.py @@ -1,7 +1,10 @@ #!/usr/bin/env python3 +import urllib.parse +import owlready2 as owl import re import shutil +import types from collections import defaultdict from jinja2 import Environment, FileSystemLoader, select_autoescape from openpyxl import load_workbook @@ -32,6 +35,19 @@ def load_file(filename, line): fields = [cell.value for cell in header] + data_properties = {} + for field in fields: + class_name = field + class_name = class_name.lower() + class_name = class_name.replace(" ", "-") + class_name = class_name.replace("/", "") + class_name = class_name.replace("(", "") + class_name = class_name.replace(")", "") + cls = types.new_class(class_name, (owl.DataProperty,)) + cls.label = "Has {}".format(field) + cls.domain = [Chip] + data_properties[field] = cls + # print("Header") # print(fields) @@ -83,6 +99,8 @@ def load_file(filename, line): # This is probably a bug in the spreadsheet. part["00 RAM"] = part["RAM Size (kB)"] if "RAM Size (kB)" in part else None + + if False: for part in parts.values(): for k, v in part.items(): @@ -93,12 +111,9 @@ def load_file(filename, line): else: print("{}: {}".format(k, v)) - if False: - break - - process_parts(parts) + return parts, data_properties -def process_parts(parts): +def process_parts(parts, data_properties): r = r"^(STM32F.|STM32H.|STM32L[012356789]|STM32L4[RS]|STM32L4|STM32WB).*" subfamily = lambda p: p["Part Number"][0:9] @@ -106,29 +121,24 @@ def process_parts(parts): # x = subfamily(p) # print("{} => {}".format(p["Part Number"], x)) - if False: - for part_number, part in parts.items(): - path = out_dir / "Chip:{}.mw".format(part_number) - with open(path, "w") as out: - template = env.get_template("mw.j2") - out.write(template.render(part=part)) - for subfamily, values in groupby(sorted(parts.values(), key=subfamily), key=subfamily): - values = list(values) -# print("{}, len={}".format(subfamily, len(values))) - write_parts(subfamily, values) + write_parts(subfamily, list(values), data_properties) -def write_parts(subfamily, parts): +def write_parts(subfamily, parts, data_properties): fields = list(next(parts.__iter__()).keys()) # [print("fieldXXX:{}".format(f)) for f in fields] print("subfamily: {}".format(subfamily)) + chip = Chip(subfamily) + chip.label = subfamily + distinct_fields = set() shared_fields = {} for field in fields: if field in distinct_fields: +# chip.setattr(data_properties[field]()) continue first = True @@ -160,9 +170,35 @@ def write_parts(subfamily, parts): parts=parts)) out_dir = Path("mw") -if out_dir.exists(): - shutil.rmtree(out_dir) -out_dir.mkdir() +owl_dir = Path("owl") + +for d in [out_dir, owl_dir]: + if d.exists(): + shutil.rmtree(d) + d.mkdir() + +base_url = "https://trygvis.io/owl/stm32" + +onto = owl.get_ontology("{}/stm32-shared.owl".format(base_url)) +shared_url = onto.base_iri +with onto: + class Chip(owl.Thing): pass + Chip.label = "Chip" + class Line(owl.DataProperty): + domain = [Chip] + range = [str] + Line.label = "Line" +with open(owl_dir / Path(onto.base_iri).name[0:-1], "wb") as f: + onto.save(f) for filename, line in files: - load_file(filename, line) + owl_file = "stm32-{}.owl".format(filename[:-5]) + url = "{}/{}".format(base_url, urllib.parse.quote(owl_file)) + + onto = owl.get_ontology(url) + with onto: + parts, data_properties = load_file(filename, line) + + process_parts(parts, data_properties) + with open(owl_dir / owl_file, "wb") as f: + onto.save(f) -- cgit v1.2.3