= Overview =

[[Part number::{{ part["Part number"] }}]] is an FPGA in the [[Chip family::Artix-7]] family from [[Manufacturer::Xilinx]].

{|class='wikitable'
!Logic Cells
|[[Xilix logic cells::{{ part["Logic Cells"] }}]]
|-
!Slices
|[[Xilix 7 series slices::{{ part["Slices"] }}]]
|-
!Distributed RAM
|[[Distributed RAM::{{ part["Max Distributed RAM (Kb)"] }} kB]]
|-
!RAM blocks
|[[RAM blocks::{{ part["36 Kb"] }}]]
|-
!RAM block size
|[[RAM block size::36 kB]]
|-
!Total RAM
|[[RAM::{{ part["Max (Kb)"] }} kB]]
|-
!Clock management tiles
|[[Xilix clock management tiles::{{ part["CMTs"] }}]]
|-
!Available IO
|[[Available IO::{{ part["Max User I/O"] }}]]
|-
!IO banks
|[[IO banks::{{ part["Total I/O Banks"] }}]]
|-
|}

= Hard cores =

{% if part["GTPs"] %}
* [[Has hard core::Gigabit transceiver;{{ part["GTPs"] }}]]
{% endif %}
{% if part["PCIe"] %}
* [[Has hard core::PCIe Gen 2;{{ part["PCIe"] }}]]
{{ "{{" }}#set: Has hard core=PCIe;{{ part["PCIe"] }} }}
{% endif %}
{% if part["XADC Blocks"] %}
* [[Has hard core::XADC;{{ part["XADC Blocks"] }}]]
{% endif %}
{% if part["DSP48E1 Slices"] %}
* [[Has hard core::DSP48E1 slice;{{ part["DSP48E1 Slices"] }}]]
{% endif %}

[[Category:Generated]]
[[Category:Xilinx Artix-7 family chip|Artix-7]]
[[Category:Artix-7 generated data set]]