= {{ part["Part number"] }} =

{|class='wikitable'
!Part number
|[[Part number::{{ part["Part number"] }}]]
|-
!Logic Cells
|[[Xilix logic cells::{{ part["Logic Cells"] }}]]
|-
!Slices
|[[Xilix 7 series slices::{{ part["Slices"] }}]]
|-
!Distributed RAM
|[[Distributed RAM::{{ part["Max Distributed RAM (Kb)"] }} kB]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::{{ part["DSP48E1 Slices"] }}]]
|-
!RAM blocks
|[[RAM blocks::{{ part["36 Kb"] }}]]
|-
!RAM
|[[RAM::{{ part["Max (Kb)"] }} kB]]
|-
!Clock management tiles
|[[Xilix clock management tiles::{{ part["CMTs"] }}]]
|-
!PCIe
|[[PCIe::{{ part["PCIe"] }}]]
|-
!GTPs
|[[GTPs::{{ part["GTPs"] }}]]
|-
!XADC Blocks
|[[XADC Blocks::{{ part["XADC Blocks"] }}]]
|-
!IO banks
|[[IO banks::{{ part["Total I/O Banks"] }}]]
|-
!Available IO
|[[Available IO::{{ part["Max User I/O"] }}]]
|-
!RAM block size
|[[RAM block size::36 kB]]
|-
|}

[[Category:Generated]]
[[Category:FPGA Chip]]
[[Category:Artix-7 generated data set]]