= XC7A12T =

== Overview ==

{|class='wikitable'
!Part number
|[[Part number::XC7A12T]]
|-
!Logic Cells
|[[Xilix logic cells::12800]]
|-
!Slices
|[[Xilix 7 series slices::2000]]
|-
!Distributed RAM
|[[Distributed RAM::171 kB]]
|-
!RAM blocks
|[[RAM blocks::20]]
|-
!RAM block size
|[[RAM block size::36 kB]]
|-
!Total RAM
|[[RAM::720 kB]]
|-
!Clock management tiles
|[[Xilix clock management tiles::3]]
|-
!Available IO
|[[Available IO::150]]
|-
!IO banks
|[[IO banks::3]]
|-
|}

== Hard cores ==

* [[Has hard core::Gigabit transceiver;2]]
* [[Has hard core::PCIe;1]]
* [[Has hard core::PCIe Gen 2;1]]
* [[Has hard core::XADC;1]]
* [[Has hard core::DSP48E1 slice;40]]

[[Category:Generated]]
[[Category:FPGA Chip]]
[[Category:Artix-7 generated data set]]