= XC7A50T =

{|class='wikitable'
!Part number
|[[Part number::XC7A50T]]
|-
!Logic Cells
|[[Xilix logic cells::52160]]
|-
!Slices
|[[Slices::8150]]
|-
!Distributed RAM
|[[Distributed RAM::600]]
|-
!DSP48E1 Slices
|[[DSP48E1 Slices::120]]
|-
!RAM blocks
|[[RAM blocks::75]]
|-
!RAM
|[[RAM::2700]]
|-
!Clock management tiles
|[[Xilix Clock management tiles::5]]
|-
!PCIe
|[[PCIe::1]]
|-
!GTPs
|[[GTPs::4]]
|-
!XADC Blocks
|[[XADC Blocks::1]]
|-
!IO banks
|[[IO banks::5]]
|-
!Max User I/O
|[[Max User I/O::250]]
|-
!RAM Block Size
|[[RAM Block Size::36 kB]]
|-
|}

[[Category:Generated]]
[[Category:FPGA Chip]]
[[Category:Artix-7 generated data set]]