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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2009-12-26 08:06:10 +0800 |
|---|---|---|
| committer | Øyvind Harboe <oyvind.harboe@zylin.com> | 2009-12-26 10:19:57 +0100 |
| commit | f9d203d1e6656041affc09528ac373a2b32497ee (patch) | |
| tree | ee9180bd6a96eacb3f318f34a56b3e8969824170 | |
| parent | 4e2b15fc93e9bd46a125449f3c1d85b774a50966 (diff) | |
| download | openocd+libswd-f9d203d1e6656041affc09528ac373a2b32497ee.tar.gz openocd+libswd-f9d203d1e6656041affc09528ac373a2b32497ee.tar.bz2 openocd+libswd-f9d203d1e6656041affc09528ac373a2b32497ee.tar.xz openocd+libswd-f9d203d1e6656041affc09528ac373a2b32497ee.zip | |
PARPORT code cleanup:
Align elements in array.
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
| -rw-r--r-- | src/jtag/drivers/parport.c | 11 |
1 files changed, 5 insertions, 6 deletions
diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c index 7ff675ba..04ac2728 100644 --- a/src/jtag/drivers/parport.c +++ b/src/jtag/drivers/parport.c @@ -76,16 +76,15 @@ struct cable { static struct cable cables[] = { - /* name tdo trst tms tck tdi srst o_inv i_inv init exit led */ + /* name tdo trst tms tck tdi srst o_inv i_inv init exit led */ { "wiggler", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80, 0x80, 0x00 }, { "wiggler2", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80, 0x00, 0x20 }, - { "wiggler_ntrst_inverted", - 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x11, 0x80, 0x80, 0x80, 0x00 }, - { "old_amt_wiggler", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x11, 0x80, 0x80, 0x80, 0x00 }, + { "wiggler_ntrst_inverted", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x11, 0x80, 0x80, 0x80, 0x00 }, + { "old_amt_wiggler", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x11, 0x80, 0x80, 0x80, 0x00 }, { "arm-jtag", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x01, 0x80, 0x80, 0x80, 0x00 }, { "chameleon", 0x80, 0x00, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00 }, - { "dlc5", 0x10, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00 }, - { "triton", 0x80, 0x08, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00 }, + { "dlc5", 0x10, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00 }, + { "triton", 0x80, 0x08, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00 }, { "lattice", 0x40, 0x10, 0x04, 0x02, 0x01, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00 }, { "flashlink", 0x20, 0x10, 0x02, 0x01, 0x04, 0x20, 0x30, 0x20, 0x00, 0x00, 0x00 }, /* Altium Universal JTAG cable. Set the cable to Xilinx Mode and wire to target as follows: |