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authorDavid Brownell <dbrownell@users.sourceforge.net>2009-12-01 01:09:10 -0800
committerDavid Brownell <dbrownell@users.sourceforge.net>2009-12-01 01:10:19 -0800
commita65e75ea34153a8d0a0fe0b07497ad75c5726ab6 (patch)
treea9a73901dc9f6bf6e05171c616729c6b992e26cb /doc
parent48edd58c3941c562a5a7ea78432a28e72108bbe4 (diff)
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Tcl and doc: update to match new 'arm mcr ...' etc
Make them match the C code. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi20
1 files changed, 19 insertions, 1 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index ea300925..7e232117 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1524,7 +1524,7 @@ proc setc15 @{regs value@} @{
echo [format "set p15 0x%04x, 0x%08x" $regs $value]
- mcr 15 [expr ($regs>>12)&0x7] \
+ arm mcr 15 [expr ($regs>>12)&0x7] \
[expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
[expr ($regs>>8)&0x7] $value
@}
@@ -5609,6 +5609,24 @@ with a handful of exceptions.
ThumbEE disassembly currently has no explicit support.
@end deffn
+@deffn Command {arm mcr} pX op1 CRn CRm op2 value
+Write @var{value} to a coprocessor @var{pX} register
+passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and using the MCR instruction.
+(Parameter sequence matches the ARM instruction, but omits
+an ARM register.)
+@end deffn
+
+@deffn Command {arm mrc} pX coproc op1 CRn CRm op2
+Read a coprocessor @var{pX} register passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and the MRC instruction.
+Returns the result so it can be manipulated by Jim scripts.
+(Parameter sequence matches the ARM instruction, but omits
+an ARM register.)
+@end deffn
+
@deffn Command {arm reg}
Display a table of all banked core registers, fetching the current value from every
core mode if necessary.