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authoroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-12 08:11:45 +0000
committeroharboe <oharboe@b42882b7-edfa-0310-969c-e2dbd0fdcd60>2009-09-12 08:11:45 +0000
commit40f361dd944803e500169337fffe7713842fd632 (patch)
treead60e121bbb07e16d7337a14efd8e7e1c8f47bc7 /tcl/target
parentc993d75d1febddc96286b0d41b682ab81bf28684 (diff)
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David Brownell <david-b@pacbell.net>
Update the board config for the DaVinci DM355 EVM so the reset-init event handler does the rest of the work it should do: - minor PLL setup bugfixes - initialize the DDR2 controller - probe both NAND banks - initialize UART0 - enable the icache git-svn-id: svn://svn.berlios.de/openocd/trunk@2699 b42882b7-edfa-0310-969c-e2dbd0fdcd60
Diffstat (limited to 'tcl/target')
-rw-r--r--tcl/target/davinci.cfg10
-rw-r--r--tcl/target/ti_dm355.cfg3
2 files changed, 12 insertions, 1 deletions
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index 07a26b21..658e7fe5 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -125,6 +125,7 @@ proc pll_v02_setup {pll_addr mult config} {
set pllstat [expr $pll_addr + 0x013c]
while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
}
+ mww [expr $pll_addr + 0x0138] 0x00
# 11 - wait at least 5 usec for reset to finish
# (assume covered by overheads including JTAG messaging)
@@ -152,7 +153,14 @@ proc psc_enable {module} {
mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
}
-# execute non-DSP PSC transition(s) set up by psc_enable
+# prepare a non-DSP module to be reset; finish with psc_go
+proc psc_reset {module} {
+ set psc_addr 0x01c41000
+ # write MDCTL
+ mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
+}
+
+# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
proc psc_go {} {
set psc_addr 0x01c41000
set ptstat_addr [expr $psc_addr + 0x0128]
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti_dm355.cfg
index da05e734..e5ef8cd2 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti_dm355.cfg
@@ -65,6 +65,9 @@ dict set dm355 a_emif_cs0 0x02000000
dict set dm355 a_emif_cs1 0x04000000
dict set dm355 ddr_emif 0x20000000
dict set dm355 ddr 0x80000000
+dict set dm355 uart0 0x01c20000
+dict set dm355 uart1 0x01c20400
+dict set dm355 uart2 0x01e06000
source [find target/davinci.cfg]