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-rw-r--r--src/target/armv7a.c2
-rw-r--r--src/target/cortex_a8.c32
-rw-r--r--src/target/xscale.c4
3 files changed, 19 insertions, 19 deletions
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 42f1c770..547a33bb 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -189,7 +189,7 @@ int armv7a_arch_state(struct target_s *target)
}
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
- "%s: 0x%8.8x pc: 0x%8.8x\n"
+ "%s: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
armv7a_state_strings[armv4_5->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 0227fabe..84ace67d 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -160,7 +160,7 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
armv7a_common_t *armv7a = armv4_5->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
- LOG_DEBUG("exec opcode 0x%08x", opcode);
+ LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
do
{
@@ -388,7 +388,7 @@ int cortex_a8_poll(target_t *target)
}
else
{
- LOG_DEBUG("Unknown target state dscr = 0x%08x", dscr);
+ LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
target->state = TARGET_UNKNOWN;
}
@@ -476,7 +476,7 @@ int cortex_a8_resume(struct target_s *target, int current,
{
resume_pc &= 0xFFFFFFFC;
}
- LOG_DEBUG("resume pc = 0x%08x", resume_pc);
+ LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).value,
0, 32, resume_pc);
@@ -516,13 +516,13 @@ int cortex_a8_resume(struct target_s *target, int current,
{
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
- LOG_DEBUG("target resumed at 0x%x", resume_pc);
+ LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
- LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
+ LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
}
dap_ap_select(swjdp, saved_apsel);
@@ -546,7 +546,7 @@ int cortex_a8_debug_entry(target_t *target)
if (armv7a->pre_debug_entry)
armv7a->pre_debug_entry(target);
- LOG_DEBUG("dscr = 0x%08x", cortex_a8->cpudbg_dscr);
+ LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
/* Examine debug reason */
switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
@@ -590,7 +590,7 @@ int cortex_a8_debug_entry(target_t *target)
cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
pc = regfile[15];
dap_ap_select(swjdp, swjdp_debugap);
- LOG_DEBUG("cpsr: %8.8x", cpsr);
+ LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
armv4_5->core_mode = cpsr & 0x3F;
@@ -668,7 +668,7 @@ void cortex_a8_post_debug_entry(target_t *target)
/* examine cp15 control reg */
armv7a->read_cp15(target, 0, 0, 1, 0, &cortex_a8->cp15_control_reg);
jtag_execute_queue();
- LOG_DEBUG("cp15_control_reg: %8.8x", cortex_a8->cp15_control_reg);
+ LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
{
@@ -827,7 +827,7 @@ int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
LOG_ERROR("JTAG failure %i", retval);
return ERROR_JTAG_DEVICE_ERROR;
}
- LOG_DEBUG("load from core reg %i value 0x%x", num, *value);
+ LOG_DEBUG("load from core reg %i value 0x%" PRIx32, num, *value);
}
else
{
@@ -880,7 +880,7 @@ int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
armv4_5->core_mode, num).valid;
return ERROR_JTAG_DEVICE_ERROR;
}
- LOG_DEBUG("write core reg %i value 0x%x", num, value);
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, value);
}
else
{
@@ -983,7 +983,7 @@ int cortex_a8_set_breakpoint(struct target_s *target,
target_write_u32(target, OMAP3530_DEBUG_BASE
+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
- LOG_DEBUG("brp %i control 0x%0x value 0x%0x", brp_i,
+ LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
brp_list[brp_i].control,
brp_list[brp_i].value);
}
@@ -1038,7 +1038,7 @@ int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint
LOG_DEBUG("Invalid BRP number in breakpoint");
return ERROR_OK;
}
- LOG_DEBUG("rbp %i control 0x%0x value 0x%0x", brp_i,
+ LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
brp_list[brp_i].control, brp_list[brp_i].value);
brp_list[brp_i].used = 0;
brp_list[brp_i].value = 0;
@@ -1330,10 +1330,10 @@ int cortex_a8_examine(struct target_s *target)
return retval;
}
- LOG_DEBUG("cpuid = 0x%08x", cpuid);
- LOG_DEBUG("ctypr = 0x%08x", ctypr);
- LOG_DEBUG("ttypr = 0x%08x", ttypr);
- LOG_DEBUG("didr = 0x%08x", didr);
+ LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
+ LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
+ LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
+ LOG_DEBUG("didr = 0x%08" PRIx32, didr);
/* Setup Breakpoint Register Pairs */
cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
diff --git a/src/target/xscale.c b/src/target/xscale.c
index cc90eb31..40126c92 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3406,10 +3406,10 @@ int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, ch
command_print(cmd_ctx, "active user-set static vectors:");
for (idx = 1; idx < 8; idx++)
if (xscale->static_low_vectors_set & (1 << idx))
- command_print(cmd_ctx, "low %d: 0x%x", idx, xscale->static_low_vectors[idx]);
+ command_print(cmd_ctx, "low %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
for (idx = 1; idx < 8; idx++)
if (xscale->static_high_vectors_set & (1 << idx))
- command_print(cmd_ctx, "high %d: 0x%x", idx, xscale->static_high_vectors[idx]);
+ command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
return ERROR_OK;
}
generated by cgit v1.2.3 (git 2.46.0) at 2024-12-23 14:37:50 +0000