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-rw-r--r--tcl/target/omap2420.cfg11
1 files changed, 6 insertions, 5 deletions
diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg
index 866b4a34..a579866e 100644
--- a/tcl/target/omap2420.cfg
+++ b/tcl/target/omap2420.cfg
@@ -8,12 +8,13 @@ if { [info exists CHIPNAME] } {
}
# NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
+reset_config srst_nogate
# Subsidiary TAP: ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
-jtag newtap $_CHIPNAME iva -irlen 4 -ircapture 0x1 -irmask 0x3f -disable
+jtag newtap $_CHIPNAME iva -irlen 4 -disable
# Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
-jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x1 -irmask 0x3f -disable
+jtag newtap $_CHIPNAME dsp -irlen 38 -disable
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID ] } {
@@ -21,7 +22,7 @@ if { [info exists ETB_TAPID ] } {
} else {
set _ETB_TAPID 0x2b900f0f
}
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
# Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
if { [info exists CPU_TAPID ] } {
@@ -29,7 +30,7 @@ if { [info exists CPU_TAPID ] } {
} else {
set _CPU_TAPID 0x07b3602f
}
-jtag newtap $_CHIPNAME arm -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
# Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
if { [info exists JRC_TAPID ] } {
@@ -37,7 +38,7 @@ if { [info exists JRC_TAPID ] } {
} else {
set _JRC_TAPID 0x01ce4801
}
-jtag newtap $_CHIPNAME jrc -irlen 2 -ircapture 0x1 -irmask 0x3 -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
# GDB target: the ARM.
set _TARGETNAME $_CHIPNAME.arm