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-rw-r--r--tcl/target/stellaris.cfg49
1 files changed, 49 insertions, 0 deletions
diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg
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+++ b/tcl/target/stellaris.cfg
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+# TI/Luminary Stellaris LM3S chip family
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lm3s
+}
+
+# CPU TAP ID 0x1ba00477 for early Sandstorm parts
+# CPU TAP ID 0x2ba00477 for later SandStorm parts, e.g. lm3s811 Rev C2
+# CPU TAP ID 0x3ba00477 for Cortex-M3 r1p2 (on Fury, DustDevil)
+# CPU TAP ID 0x4ba00477 for Cortex-M3 r2p0 (on Tempest)
+# ... we'll ignore the JTAG version field, rather than list every
+# chip revision that turns up.
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x0ba00477
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -irmask 0xf \
+ -expected-id $_CPUTAPID -ignore-version
+
+# The "lm3s" variant uses a software reset rather than SRST.
+# This stops the debug registers from being cleared; it works
+# around an erratum which should be fixed in later silicon.
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu \
+ -variant lm3s
+
+# 8K working area at base of ram, not backed up
+#
+# NOTE: you may need or want to reconfigure the work area;
+# some parts have just 6K, and you may want to use other
+# addresses (at end of mem not beginning) or back it up.
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
+
+# JTAG speed ... slow enough to work with a 12 MHz RC oscillator;
+# LM3S parts don't support RTCK
+#
+# NOTE: this may be increased by a reset-init handler, after it
+# configures and enables the PLL. Or you might need to decrease
+# this, if you're using a slower clock.
+jtag_khz 500
+$_TARGETNAME configure -event reset-start {jtag_khz 500}
+
+# flash configuration ... autodetects sizes, autoprobed
+flash bank $_CHIPNAME.flash stellaris 0 0 0 0 $_TARGETNAME
+