diff options
| -rw-r--r-- | src/target/arm11.c | 11 | ||||
| -rw-r--r-- | src/target/arm11.h | 12 | ||||
| -rw-r--r-- | src/target/arm11_dbgtap.c | 4 |
3 files changed, 20 insertions, 7 deletions
diff --git a/src/target/arm11.c b/src/target/arm11.c index f6700b29..45066031 100644 --- a/src/target/arm11.c +++ b/src/target/arm11.c @@ -282,7 +282,6 @@ enum arm11_regcache_ids ARM11_RC_WDTR, ARM11_RC_RDTR, - ARM11_RC_MAX, }; @@ -562,7 +561,7 @@ void arm11_leave_debug_state(arm11_common_t * arm11) /* MRC p14,0,r?,c0,c5,0 */ arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i)); -// DEBUG("RESTORE R%d %08x", i, R(RX + i)); +// DEBUG("RESTORE R" ZU " %08x", i, R(RX + i)); }} arm11_run_instr_data_finish(arm11); @@ -788,7 +787,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b if (!current) R(PC) = address; - INFO("RESUME PC %08x", R(PC)); + INFO("RESUME PC %08x%s", R(PC), !current ? "!" : ""); /* clear breakpoints/watchpoints and VCR*/ arm11_sc7_clear_vbw(arm11); @@ -827,7 +826,7 @@ int arm11_resume(struct target_s *target, int current, u32 address, int handle_b arm11_sc7_run(arm11, brp, asizeof(brp)); - DEBUG("Add BP %zd at %08x", brp_num, bp->address); + DEBUG("Add BP " ZU " at %08x", brp_num, bp->address); brp_num++; } @@ -885,7 +884,7 @@ int arm11_step(struct target_s *target, int current, u32 address, int handle_bre if (!current) R(PC) = address; - INFO("STEP PC %08x", R(PC)); + INFO("STEP PC %08x%s", R(PC), !current ? "!" : ""); /** \todo TODO: Thumb not supported here */ @@ -1518,7 +1517,7 @@ void arm11_build_reg_cache(target_t *target) ARM11_REGCACHE_COUNT != asizeof(arm11_reg_defs) || ARM11_REGCACHE_COUNT != ARM11_RC_MAX) { - ERROR("arm11->reg_values inconsistent (%d %zd %zd %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX); + ERROR("arm11->reg_values inconsistent (%d " ZU " " ZU " %d)", ARM11_REGCACHE_COUNT, asizeof(arm11->reg_values), asizeof(arm11_reg_defs), ARM11_RC_MAX); exit(-1); } diff --git a/src/target/arm11.h b/src/target/arm11.h index 638c2ca9..c2607a6d 100644 --- a/src/target/arm11.h +++ b/src/target/arm11.h @@ -33,6 +33,18 @@ type * variable = calloc(1, sizeof(type) * items) +/* Don't know exactly when %zu was added to glibc (CVS says in 1998). + Assume for now that its between GCC versions 3.x.x and 4.x.x . + MinGW's GCC 3.4.5 comes with a glibc that doesn't support it. +*/ + +#if __GNUC__ > 3 +#define ZU "%zu" +#else +#define ZU "%u" +#endif + + #define ARM11_REGCACHE_MODEREGS 0 #define ARM11_REGCACHE_FREGS 0 diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c index 0dcc2d0b..bb4695e0 100644 --- a/src/target/arm11_dbgtap.c +++ b/src/target/arm11_dbgtap.c @@ -521,7 +521,7 @@ void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 }} if (error_count) - ERROR("Transfer errors %d", error_count); + ERROR("Transfer errors " ZU, error_count); } @@ -739,6 +739,8 @@ void arm11_sc7_clear_vbw(arm11_common_t * arm11) } (pos++)->address = ARM11_SC7_VCR; + + arm11_sc7_run(arm11, clear_bw, asizeof(clear_bw)); } /** Write VCR register |