diff options
Diffstat (limited to 'src/target/etm.h')
| -rw-r--r-- | src/target/etm.h | 131 |
1 files changed, 127 insertions, 4 deletions
diff --git a/src/target/etm.h b/src/target/etm.h index 4b24e5c8..59591788 100644 --- a/src/target/etm.h +++ b/src/target/etm.h @@ -1,7 +1,10 @@ /***************************************************************************
- * Copyright (C) 2005 by Dominic Rath *
+ * Copyright (C) 2005, 2007 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
+ * Copyright (C) 2007 by Vincent Palatin *
+ * vincent.palatin_openocd@m4x.org *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -20,11 +23,14 @@ #ifndef ETM_H
#define ETM_H
+#include "trace.h"
#include "target.h"
#include "register.h"
#include "arm_jtag.h"
-// ETM registers (V1.2 protocol)
+#include "armv4_5.h"
+
+/* ETM registers (V1.3 protocol) */
enum
{
ETM_CTRL = 0x00,
@@ -58,14 +64,123 @@ enum ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
};
-
typedef struct etm_reg_s
{
int addr;
arm_jtag_t *jtag_info;
} etm_reg_t;
-extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, int extra_reg);
+typedef enum
+{
+ /* Port width */
+ ETM_PORT_4BIT = 0x00,
+ ETM_PORT_8BIT = 0x10,
+ ETM_PORT_16BIT = 0x20,
+ ETM_PORT_WIDTH_MASK = 0x70,
+ /* Port modes */
+ ETM_PORT_NORMAL = 0x00000,
+ ETM_PORT_MUXED = 0x10000,
+ ETM_PORT_DEMUXED = 0x20000,
+ ETM_PORT_MODE_MASK = 0x30000,
+ /* Clocking modes */
+ ETM_PORT_FULL_CLOCK = 0x0000,
+ ETM_PORT_HALF_CLOCK = 0x1000,
+ ETM_PORT_CLOCK_MASK = 0x1000,
+} etm_portmode_t;
+
+typedef enum
+{
+ /* Data trace */
+ ETMV1_TRACE_NONE = 0x00,
+ ETMV1_TRACE_DATA = 0x01,
+ ETMV1_TRACE_ADDR = 0x02,
+ ETMV1_TRACE_MASK = 0x03,
+ /* ContextID */
+ ETMV1_CONTEXTID_NONE = 0x00,
+ ETMV1_CONTEXTID_8 = 0x10,
+ ETMV1_CONTEXTID_16 = 0x20,
+ ETMV1_CONTEXTID_32 = 0x30,
+ ETMV1_CONTEXTID_MASK = 0x30,
+ /* Misc */
+ ETMV1_CYCLE_ACCURATE = 0x100
+} etmv1_tracemode_t;
+
+/* forward-declare ETM context */
+struct etm_context_s;
+
+typedef struct etm_capture_driver_s
+{
+ char *name;
+ int (*register_commands)(struct command_context_s *cmd_ctx);
+ int (*init)(struct etm_context_s *etm_ctx);
+ trace_status_t (*status)(struct etm_context_s *etm_ctx);
+ int (*read_trace)(struct etm_context_s *etm_ctx);
+ int (*start_capture)(struct etm_context_s *etm_ctx);
+ int (*stop_capture)(struct etm_context_s *etm_ctx);
+} etm_capture_driver_t;
+
+typedef struct etmv1_trace_data_s
+{
+ u8 pipestat; /* pipeline cycle this packet belongs to */
+ u16 packet; /* packet data (4, 8 or 16 bit) */
+ int tracesync; /* 1 if tracesync was set on this packet */
+} etmv1_trace_data_t;
+
+/* describe a trace context
+ * if support for ETMv2 or ETMv3 is to be implemented,
+ * this will have to be split into version independent elements
+ * and a version specific part
+ */
+typedef struct etm_context_s
+{
+ reg_cache_t *reg_cache; /* ETM register cache */
+ etm_capture_driver_t *capture_driver; /* driver used to access ETM data */
+ void *capture_driver_priv; /* capture driver private data */
+ trace_status_t capture_status; /* current state of capture run */
+ etmv1_trace_data_t *trace_data; /* trace data */
+ u32 trace_depth; /* number of trace cycles to be analyzed, 0 if no trace data available */
+ etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
+ etmv1_tracemode_t tracemode; /* type of information the trace contains (data, addres, contextID, ...) */
+ armv4_5_state_t core_state; /* current core state (ARM, Thumb, Jazelle) */
+// trace_image_provider_t image_provider; /* source for target opcodes */
+ u32 pipe_index; /* current trace cycle */
+ u32 data_index; /* cycle holding next data packet */
+ u32 current_pc; /* current program counter */
+ u32 pc_ok; /* full PC has been acquired */
+ u32 last_branch; /* last branch address output */
+ u32 last_ptr; /* address of the last data access */
+ u32 context_id; /* context ID of the code being traced */
+} etm_context_t;
+
+/* PIPESTAT values */
+typedef enum
+{
+ STAT_IE = 0x0,
+ STAT_ID = 0x1,
+ STAT_IN = 0x2,
+ STAT_WT = 0x3,
+ STAT_BE = 0x4,
+ STAT_BD = 0x5,
+ STAT_TR = 0x6,
+ STAT_TD = 0x7
+} etmv1_pipestat_t;
+
+/* branch reason values */
+typedef enum
+{
+ BR_NORMAL = 0x0, /* Normal PC change : periodic synchro (ETMv1.1) */
+ BR_ENABLE = 0x1, /* Trace has been enabled */
+ BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
+ BR_NODEBUG = 0x3, /* ARM has exited for debug state */
+ BR_PERIOD = 0x4, /* Peridioc synchronization point (ETM>=v1.2)*/
+ BR_RSVD5 = 0x5, /* reserved */
+ BR_RSVD6 = 0x6, /* reserved */
+ BR_RSVD7 = 0x7, /* reserved */
+} etmv1_branch_reason_t;
+
+extern char *etmv1v1_branch_reason_strings[];
+
+extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
extern int etm_read_reg(reg_t *reg);
extern int etm_write_reg(reg_t *reg, u32 value);
extern int etm_read_reg_w_check(reg_t *reg, u8* check_value, u8* check_mask);
@@ -73,4 +188,12 @@ extern int etm_store_reg(reg_t *reg); extern int etm_set_reg(reg_t *reg, u32 value);
extern int etm_set_reg_w_exec(reg_t *reg, u8 *buf);
+int etm_register_commands(struct command_context_s *cmd_ctx);
+int etm_register_user_commands(struct command_context_s *cmd_ctx);
+extern etm_context_t* etm_create_context(etm_portmode_t portmode, char *capture_driver_name);
+
+#define ERROR_ETM_INVALID_DRIVER (-1300)
+#define ERROR_ETM_PORTMODE_NOT_SUPPORTED (-1301)
+#define ERROR_ETM_CAPTURE_INIT_FAILED (-1302)
+
#endif /* ETM_H */
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