diff options
Diffstat (limited to 'src/target/target')
| -rw-r--r-- | src/target/target/at91sam9260.cfg | 33 | ||||
| -rw-r--r-- | src/target/target/nslu2.cfg | 22 | ||||
| -rw-r--r-- | src/target/target/pxa255.cfg | 86 | ||||
| -rw-r--r-- | src/target/target/pxa255_sst.cfg | 13 | ||||
| -rw-r--r-- | src/target/target/zy1000.cfg | 30 |
5 files changed, 184 insertions, 0 deletions
diff --git a/src/target/target/at91sam9260.cfg b/src/target/target/at91sam9260.cfg new file mode 100644 index 00000000..ca5c0e19 --- /dev/null +++ b/src/target/target/at91sam9260.cfg @@ -0,0 +1,33 @@ +# Thanks to Pieter Conradie for this script!
+# Target: Atmel AT91SAM9260
+######################################
+
+reset_config trst_and_srst
+
+#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
+jtag_device 4 0x1 0xf 0xe
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 0
+
+######################
+# Target configuration
+######################
+
+#target <type> <endianess> <reset mode> <JTAG pos> <variant>
+target arm926ejs little reset_init 0 arm926ejs
+
+target_script 0 reset event/at91sam9260_reset.script
+run_and_halt_time 0 30
+
+#working area <target#> <address> <size> <backup|nobackup>
+working_area 0 0x00300000 0x1000 backup
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x10000000 0x01000000 2 2 0
+
diff --git a/src/target/target/nslu2.cfg b/src/target/target/nslu2.cfg new file mode 100644 index 00000000..ba6a7973 --- /dev/null +++ b/src/target/target/nslu2.cfg @@ -0,0 +1,22 @@ +# use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only
+
+# jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 7 0x1 0x7f 0x7e
+
+# target configuration
+target xscale big reset_init 0 ixp42x
+run_and_halt_time 0 30
+
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+working_area 0 0x00020000 0x10000 nobackup
+
+# flash bank <driver> <base> <size> <chip_width> <bus_width>
+#flash bank cfi 0x50000000 0x1000000 2 4 0
+
+
+
+
+
diff --git a/src/target/target/pxa255.cfg b/src/target/target/pxa255.cfg new file mode 100644 index 00000000..6666309d --- /dev/null +++ b/src/target/target/pxa255.cfg @@ -0,0 +1,86 @@ +jtag_device 5 0x1 0x1f 0x1e
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+target xscale little reset_init 0 pxa255
+reset_config trst_and_srst
+run_and_halt_time 0 30
+
+target_script 0 reset /ram/pxa255.init
+
+#xscale debug_handler 0 0xFFFF0800 # debug handler base address
+
+trunc /ram/pxa255.init
+append /ram/pxa255.init #configuration file for PXA250 Evaluation Board
+append /ram/pxa255.init # -----------------------------------------------------
+append /ram/pxa255.init #
+append /ram/pxa255.init xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
+append /ram/pxa255.init #
+append /ram/pxa255.init # setup GPIO
+append /ram/pxa255.init #
+append /ram/pxa255.init mww 0x40E00018 0x00008000 #CPSR0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E0001C 0x00000002 #GPSR1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00020 0x00000008 #GPSR2
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E0000C 0x00008000 #GPDR0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00054 0x80000000 #GAFR0_L
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00058 0x00188010 #GAFR0_H
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E0005C 0x60908018 #GAFR1_L
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E0000C 0x0280E000 #GPDR0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00010 0x821C88B2 #GPDR1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00014 0x000F03DB #GPDR2
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x40E00000 0x000F03DB #GPLR0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
+append /ram/pxa255.init
+append /ram/pxa255.init mww 0x40F00004 0x00000020 #PSSR
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
+append /ram/pxa255.init #
+append /ram/pxa255.init # setup memory controller
+append /ram/pxa255.init #
+append /ram/pxa255.init mww 0x48000008 0x01111998 #MSC0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000010 0x00047ff0 #MSC2
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000014 0x00000000 #MECR
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000028 0x00010504 #MCMEM0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x4800002C 0x00010504 #MCMEM1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000030 0x00010504 #MCATT0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000034 0x00010504 #MCATT1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000038 0x00004715 #MCIO0
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x4800003C 0x00004715 #MCIO1
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init #
+append /ram/pxa255.init mww 0x48000004 0x03CA4018 #MDREF
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000004 0x004B4018 #MDREF
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000004 0x000B4018 #MDREF
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000004 0x000BC018 #MDREF
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000000 0x00001AC8 #MDCNFG
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
+append /ram/pxa255.init mww 0x48000000 0x00001AC9 #MDCNFG
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init mww 0x48000040 0x00000000 #MDMRS
+append /ram/pxa255.init sleep 20
+append /ram/pxa255.init
diff --git a/src/target/target/pxa255_sst.cfg b/src/target/target/pxa255_sst.cfg new file mode 100644 index 00000000..79522f2d --- /dev/null +++ b/src/target/target/pxa255_sst.cfg @@ -0,0 +1,13 @@ +# A PXA255 test board with SST 39LF400A flash
+#
+# At reset the memory map is as follows. Note that
+# the memory map changes later on as the application
+# starts...
+#
+# RAM at 0x40000000
+# Flash at 0x00000000
+#
+script /target/pxa255.cfg
+# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
+flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
+working_area 0 0x4000000 0x4000 nobackup 0
diff --git a/src/target/target/zy1000.cfg b/src/target/target/zy1000.cfg new file mode 100644 index 00000000..e6929f22 --- /dev/null +++ b/src/target/target/zy1000.cfg @@ -0,0 +1,30 @@ +#Script for ZY1000
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+
+#target configuration
+#target arm7tdmi <endianness> <reset mode> <chainpos> <variant>
+target arm7tdmi little reset_init 0 arm7tdmi-s_r4
+
+# at CPU CLK <32kHz this must be disabled
+arm7 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+
+flash bank ecosflash 0x01000000 0x200000 2 2 0 /rom/at91eb40a.elf
+target_script 0 reset event/zy1000_reset.script
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+working_area 0 0x00000000 0x20000 nobackup
|