diff options
Diffstat (limited to 'src/target/target')
49 files changed, 1224 insertions, 394 deletions
diff --git a/src/target/target/aduc702x.cfg b/src/target/target/aduc702x.cfg index c9ef92cd..35f5ff32 100644 --- a/src/target/target/aduc702x.cfg +++ b/src/target/target/aduc702x.cfg @@ -1,6 +1,27 @@ ## -*- tcl -*- ## + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2410 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # This config file was defaulting to big endian.. + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0xffffffff +} + + jtag_nsrst_delay 200 jtag_ntrst_delay 200 @@ -10,18 +31,13 @@ reset_config none ## JTAG scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID ## ## Target configuration ## -target create target0 arm7tdmi -endian little -chain-position 0 - -## software initiated reset (if your SRST isn't wired) -#proc target_0_reset {} { mwb 0x0ffff0230 04 } - -# use top 1k of SRAM for as temporary JTAG memory -#[new_target_name] configure -work-area-virt 0 -work-area-phys 0x11C00 -work-area-size 0x400 -work-area-backup 1 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME ## flash configuration flash bank aduc702x 0x80000 0x10000 2 2 0 @@ -37,5 +53,5 @@ proc watchdog_service {} { set watchdog_hdl [after 500 watchdog_service] } -[new_target_name] configure -event reset-halt-post { watchdog_service } -[new_target_name] configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl } +$_TARGETNAME configure -event reset-halt-post { watchdog_service } +$_TARGETNAME configure -event old-pre_resume { global watchdog_hdl; after cancel $watchdog_hdl } diff --git a/src/target/target/at91eb40a.cfg b/src/target/target/at91eb40a.cfg index b2b91dbc..c552dc5b 100644 --- a/src/target/target/at91eb40a.cfg +++ b/src/target/target/at91eb40a.cfg @@ -1,5 +1,25 @@ #Script for AT91EB40a +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91eb40a +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + + #Atmel ties SRST & TRST together, at which point it makes #no sense to use TRST, but use TMS instead. # @@ -11,10 +31,11 @@ reset_config srst_only srst_pulls_trst #jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID #target configuration -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 # speed up memory downloads arm7_9 fast_memory_access enable @@ -25,9 +46,9 @@ flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf # required for usable performance. Used for lots of # other things than flash programming. -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00030000 -work-area-size 0x10000 -work-area-backup 0 -[new_target_name] configure -event reset-init { +$_TARGETNAME configure -event reset-init { puts "Running reset init script for AT91EB40A" # Reset script for AT91EB40a reg cpsr 0x000000D3 diff --git a/src/target/target/at91r40008.cfg b/src/target/target/at91r40008.cfg index 0d323af5..48317c86 100644 --- a/src/target/target/at91r40008.cfg +++ b/src/target/target/at91r40008.cfg @@ -1,3 +1,24 @@ + + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at9r40008 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + jtag_nsrst_delay 200 jtag_ntrst_delay 200 @@ -6,12 +27,12 @@ reset_config srst_only srst_pulls_trst #jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe - -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGENAME -variant arm7tdmi -[new_target_name] configure -event gdb-flash-erase-start { +$_TARGETNAME configure -event gdb-flash-erase-start { wait_halt sleep 10 poll @@ -21,7 +42,7 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm mww 0xffe00020 0x00000001 } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0 flash bank cfi 0x10000000 0x400000 2 2 0 diff --git a/src/target/target/at91rm9200.cfg b/src/target/target/at91rm9200.cfg new file mode 100755 index 00000000..58c7318e --- /dev/null +++ b/src/target/target/at91rm9200.cfg @@ -0,0 +1,51 @@ + +reset_config trst_and_srst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91rm9200 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x05b0203f +} + +# Never allow the following! +if { $_CPUTAPID == 0x15b0203f } { + puts "-------------------------------------------------------" + puts "- ERROR: -" + puts "- ERROR: TapID 0x15b0203f is wrong for at91rm9200 -" + puts "- ERROR: The chip/board has a JTAG select pin/jumper -" + puts "- ERROR: -" + puts "- ERROR: In one position (0x05b0203f) it selects the -" + puts "- ERROR: ARM CPU, in the other position (0x1b0203f) -" + puts "- ERROR: it selects boundry-scan not the ARM -" + puts "- ERROR: -" + puts "-------------------------------------------------------" +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + +# Create the GDB Target. +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME +# AT91RM9200 has a 16K block of sram @ 0x0020.0000 +$_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1 + +# This chip has a DCC ... use it +arm7_9 dcc_downloads enable + + + + + diff --git a/src/target/target/at91sam9260.cfg b/src/target/target/at91sam9260.cfg index b3e1d215..d7c8833c 100644 --- a/src/target/target/at91sam9260.cfg +++ b/src/target/target/at91sam9260.cfg @@ -2,21 +2,16 @@ # Target: Atmel AT91SAM9260 ###################################### -reset_config trst_and_srst - -#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction> -jtag_device 4 0x1 0xf 0xe - -jtag_nsrst_delay 200 -jtag_ntrst_delay 0 +# We add to the minimal configuration. +source [find target/at91sam9260minimal.cfg] ###################### # Target configuration ###################### -target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs - -[new_target_name] configure -event reset-init { +$_TARGET_NAME configure -event reset-init { + # at reset chip runs at 32khz + jtag_khz 8 mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog @@ -31,7 +26,8 @@ target create target0 arm926ejs -endian little -chain-position 0 -variant arm926 mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected sleep 10 # wait 10 ms - jtag_speed 0 # Increase JTAG Speed to 6 MHz + # Now run at anything fast... ie: 10mhz! + jtag_khz 10000 # Increase JTAG Speed to 6 MHz arm7_9 dcc_downloads enable # Enable faster DCC downloads mww 0xffffec00 0x01020102 # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit @@ -76,7 +72,6 @@ target create target0 arm926ejs -endian little -chain-position 0 -variant arm926 mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1 ##################### # Flash configuration diff --git a/src/target/target/at91sam9260minimal.cfg b/src/target/target/at91sam9260minimal.cfg index ca6edd9b..93114d80 100644 --- a/src/target/target/at91sam9260minimal.cfg +++ b/src/target/target/at91sam9260minimal.cfg @@ -2,10 +2,29 @@ # Target: Atmel AT91SAM9260 ###################################### +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME at91sam9260 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + reset_config trst_and_srst -#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction> -jtag_device 4 0x1 0xf 0xe +# +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID jtag_nsrst_delay 200 jtag_ntrst_delay 200 @@ -14,6 +33,10 @@ jtag_ntrst_delay 200 # Target configuration ###################### -target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs + +# Internal sram1 memory +$_TARGET_NAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1 diff --git a/src/target/target/eir-sam7se512.cfg b/src/target/target/eir-sam7se512.cfg deleted file mode 100644 index bf53be1f..00000000 --- a/src/target/target/eir-sam7se512.cfg +++ /dev/null @@ -1,106 +0,0 @@ -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only srst_pulls_trst - -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe - -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi - - -[new_target_name] configure -event reset-init { - # WDT_MR, disable watchdog - mww 0xFFFFFD44 0x00008000 - - # RSTC_MR, enable user reset - mww 0xfffffd08 0xa5000001 - - # CKGR_MOR - mww 0xFFFFFC20 0x00000601 - sleep 10 - - # CKGR_PLLR - mww 0xFFFFFC2C 0x00481c0e - sleep 10 - - # PMC_MCKR - mww 0xFFFFFC30 0x00000007 - sleep 10 - - # PMC_IER - mww 0xFFFFFF60 0x00480100 - - # - # Enable SDRAM interface. - # - - # Enable SDRAM control at PIO A. - mww 0xfffff474 0x3f800000 # PIO_BSR_OFF - mww 0xfffff404 0x3f800000 # PIO_PDR_OFF - - # Enable address bus (A0, A2-A11, A13-A17) at PIO B - mww 0xfffff674 0x0003effd # PIO_BSR_OFF - mww 0xfffff604 0x0003effd # PIO_PDR_OFF - - # Enable 16 bit data bus at PIO C - mww 0xfffff870 0x0000ffff # PIO_ASR_OFF - mww 0xfffff804 0x0000ffff # PIO_PDR_OFF - - # Enable SDRAM chip select - mww 0xffffff80 0x00000002 # EBI_CSA_OFF - - # Set SDRAM characteristics in configuration register. - # Hard coded values for MT48LC32M16A2 with 48MHz CPU. - mww 0xffffffb8 0x2192215a # SDRAMC_CR_OFF - sleep 10 - - # Issue 16 bit SDRAM command: NOP - mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - - # Issue 16 bit SDRAM command: Precharge all - mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - - # Issue 8 auto-refresh cycles - mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF - mww 0x20000000 0x00000000 - - # Issue 16 bit SDRAM command: Set mode register - mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF - mww 0x20000014 0xcafedede - - # Set refresh rate count ??? - mww 0xffffffb4 0x00000013 # SDRAMC_TR_OFF - - # Issue 16 bit SDRAM command: Normal mode - mww 0xffffffb0 0x00000010 # SDRAMC_MR_OFF - mww 0x20000000 0x00000180 - - # - # Enable external reset key. - # - mww 0xfffffd08 0xa5000001 -} - -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 - -#flash bank <driver> <base> <size> <chip_width> <bus_width> -flash bank at91sam7 0 0 0 0 0 - -# For more information about the configuration files, take a -# look at the "Open On-Chip Debugger (openocd)" documentation. diff --git a/src/target/target/epc9301.cfg b/src/target/target/epc9301.cfg index 31ff3320..6dbb91b3 100644 --- a/src/target/target/epc9301.cfg +++ b/src/target/target/epc9301.cfg @@ -1,9 +1,30 @@ # Cirrus Logic EP9301 processor on an Olimex CS-E9301 board. -jtag_device 4 0x1 0xf 0xe + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ep9301 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID jtag_nsrst_delay 100 jtag_ntrst_delay 100 -target create target0 arm920t -endian little -chain-position 0 -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1 #flash configuration #flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...] diff --git a/src/target/target/hammer.cfg b/src/target/target/hammer.cfg deleted file mode 100644 index 441f7abf..00000000 --- a/src/target/target/hammer.cfg +++ /dev/null @@ -1,47 +0,0 @@ -# Target Configuration for the TinCanTools S3C2410 Based Hammer Module -# http://www.tincantools.com - -#use combined on interfaces or targets that can't set TRST/SRST separately -reset_config trst_and_srst - -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe - - -target create target0 arm920t -endian little -chain-position 0 -variant arm920t -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0 -[new_target_name] configure -event reset-init { - # Reset Script for the TinCanTools S3C2410 Based Hammer Module - # http://www.tincantools.com - # - # Setup primary clocks and initialize the SDRAM - mww 0x53000000 0x00000000 - mww 0x4a000008 0xffffffff - mww 0x4a00000c 0x000007ff - mww 0x4c000000 0x00ffffff - mww 0x4c000014 0x00000003 - mww 0x4c000004 0x000a1031 - mww 0x48000000 0x11111122 - mww 0x48000004 0x00000700 - mww 0x48000008 0x00000700 - mww 0x4800000c 0x00000700 - mww 0x48000010 0x00000700 - mww 0x48000014 0x00000700 - mww 0x48000018 0x00000700 - mww 0x4800001c 0x00018005 - mww 0x48000020 0x00018005 - mww 0x48000024 0x009c0459 - mww 0x48000028 0x000000b2 - mww 0x4800002c 0x00000030 - mww 0x48000030 0x00000030 - flash probe 0 -} - -# speed up memory downloads -arm7_9 fast_memory_access enable -arm7_9 dcc_downloads enable - -#flash configuration -#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...] -flash bank cfi 0x00000000 0x1000000 2 2 0 diff --git a/src/target/target/imote2.cfg b/src/target/target/imote2.cfg index a02a8d3c..beb539b6 100644 --- a/src/target/target/imote2.cfg +++ b/src/target/target/imote2.cfg @@ -1,5 +1,24 @@ # iMote2 # +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imote2 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + # PXA271 and an Intel Strataflash of 32 Megabytes (p30) # # Marvell/Intel PXA270 Script @@ -9,15 +28,18 @@ jtag_nsrst_delay 800 # set the jtag_ntrst_delay to the delay introduced by a reset circuit # the rest of the needed delays are built into the openocd program jtag_ntrst_delay 0 -#use combined on interfaces or targets that can’t set TRST/SRST separately +#use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst separate #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 7 0x1 0x7f 0x7e -target xscale little 0 pxa27x + +jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -varient pxa27x +$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1 # maps to PXA internal RAM. If you are using a PXA255 # you must initialize SDRAM or leave this option off -working_area 0 0x5c000000 0x10000 nobackup + #flash bank <driver> <base> <size> <chip_width> <bus_width> # works for P30 flash diff --git a/src/target/target/imx27.cfg b/src/target/target/imx27.cfg index c6fdf41c..240a8498 100644 --- a/src/target/target/imx27.cfg +++ b/src/target/target/imx27.cfg @@ -1,12 +1,42 @@ #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst -# There are 2 taps on the chip: -# The ETM -jtag_device 4 0x1 0xf 0xe -# The ARM926EJS -jtag_device 4 0x1 0xf 0xe +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx27 +} -# Note above there are 2 taps (#0 and #1) the ARM926 is the 2nd tap (ie #1) -target create target0 arm926ejs -endianess little -chain-position 1 -variant arm926ejs +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Note above there are 2 taps + +# The bs tap +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + set _BSTAPID 0x1b900f0f +} +jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_BSTAPID + +# The CPU tap +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x07926121 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# Create the GDB Target. +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs +$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size 0x8000 -work-area-backup 1 +# Internal to the chip, there is 45K of SRAM +# + +arm7_9 dcc_downloads enable diff --git a/src/target/target/imx31.cfg b/src/target/target/imx31.cfg index 34b35d8b..83a4abc4 100644 --- a/src/target/target/imx31.cfg +++ b/src/target/target/imx31.cfg @@ -2,18 +2,64 @@ # # NB! Does not work yet. Work in progress -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -# 4 devices otherwise openocd complains, the last one returns 0x0 for all bytes -jtag_device 4 0x1 0x0 0xe -jtag_device 5 0x1 0x1f 0x1e -#jtag_device 4 0x0 0x0 0xe -# The device below does not have an IDCODE, so lsb is 1 -jtag_device 4 0x0 0x0 0xf -jtag_device 5 0x1 0x0 0x1e +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME imx31 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + +#======================================== +# The "system jtag controller" +# IMX31 reference manual, page 6-28 - figure 6-14 +if { [info exists SJCTAPID ] } { + set _SJCTAPID $SJCTAPID +} else { + set _SJCTAPID 0xffffffff +} +jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 00 irmask 0x0 -expected-id $_SJCTAPID + +# The "SDMA" - <S>mart <DMA> controller debug tap +# Based on some IO pins - this can be disabled & removed +# See diagram: 6-14 +# SIGNAL NAME: +# SJC_MOD - controls multiplexer - disables ARM1136 +# SDMA_BYPASS - disables SDMA - +# +if { [info exists SDMATAPID ] } { + set _SDMATAPID $SDMATAPID +} else { + set _SDMATAPID 0xffffffff +} +# Per section 40.17.1, table 40-85 the IR register is 4 bits +# But this conflicts with Diagram 6-13, "3bits ir and drs" +jtag newtap $_CHIPNAME smda -irlen 4 -ircapture 0xe -irmask 0xf -expected-id $_SJCTAPID + +# The ARM11 core tap +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0xffffffff +} +# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1e irmask 0x1f -expected-id $_SJCTAPID + jtag_nsrst_delay 500 jtag_ntrst_delay 500 -target create target0 arm11 -endian little -chain-position 1 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME diff --git a/src/target/target/ipx42x.cfg b/src/target/target/ipx42x.cfg index f2185f80..961a5c93 100644 --- a/src/target/target/ipx42x.cfg +++ b/src/target/target/ipx42x.cfg @@ -1,9 +1,32 @@ #xscale ixp42x CPU + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ipx42x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN big +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + #use combined on interfaces or targets that can?t set TRST/SRST separately reset_config srst_only srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 7 0x1 0x7f 0x7e -target create target0 xscale -endian big -chain-position 0 -variant IXP42x + +jtag newtap $_CPUNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ipxP42x diff --git a/src/target/target/is5114.cfg b/src/target/target/is5114.cfg index 56c8685c..95736c29 100644 --- a/src/target/target/is5114.cfg +++ b/src/target/target/is5114.cfg @@ -1,20 +1,49 @@ # script for Insilica IS-5114 +# AKA: Atmel AT76C114 - an ARM946 chip +# ATMEL sold his product line to Insilica... + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME is5114 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a little endian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} # jtag speed. We need to stick to 16kHz until we've finished reset. jtag_rclk 16 reset_config trst_and_srst -jtag_device 8 0x1 0x1 0xfe -jtag_device 4 0x1 0xf 0xe -jtag_device 5 0x1 0x1 0x1e +# Do not specify a tap id here... +#OLD SYNTAX: jtag_device 8 0x1 0x1 0xfe +jtag newtap $_CHIPNAME unknown1 -irlen 8 -ircapture 0x01 -irmask 1 +#OLD SYNTAX: jtag_device 4 0x1 0xf 0xe +# This is the "arm946" chip. +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x0e -irmask 0xf +#OLD SYNTAX: jtag_device 5 0x1 0x1 0x1e +jtag newtap $_CHIPNAME unknown2 -irlen 5 -ircapture 1 -irmask 1 + #arm946e-s and -target arm966e little 1 arm966e +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -varient arm966e -[new_target_name] configure -event reset-start { jtag_rclk 16 } -[new_target_name] configure -event reset-init { +$_TARGETNAME configure -event reset-start { jtag_rclk 16 } +$_TARGETNAME configure -event reset-init { # We can increase speed now that we know the target is halted. jtag_rclk 3000 } -working_area 0 0x50000000 16384 nobackup +$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1 diff --git a/src/target/target/lm3s3748.cfg b/src/target/target/lm3s3748.cfg index bb35181c..f3ed12e2 100644 --- a/src/target/target/lm3s3748.cfg +++ b/src/target/target/lm3s3748.cfg @@ -3,6 +3,26 @@ # NB! work in progress! Duplicated from lm3s811.cfg, but does # it need modification?? +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lm3s3748 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a little endian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + # RCLK jtag_khz 500 @@ -13,16 +33,17 @@ jtag_ntrst_delay 100 reset_config srst_only #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID + # the luminary variant causes a software reset rather than asserting SRST # this stops the debug registers from being cleared # this will be fixed in later revisions of silicon -target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s # 8k working area at base of ram -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0 #flash configuration flash bank stellaris 0 0 0 0 0 diff --git a/src/target/target/lm3s6965.cfg b/src/target/target/lm3s6965.cfg index e1d38227..8fdc9c89 100644 --- a/src/target/target/lm3s6965.cfg +++ b/src/target/target/lm3s6965.cfg @@ -1,5 +1,26 @@ # script for luminary lm3s6965 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lm3s6965 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a little endian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + # jtag speed jtag_khz 500 @@ -10,16 +31,17 @@ jtag_ntrst_delay 100 reset_config srst_only #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID + # the luminary variant causes a software reset rather than asserting SRST # this stops the debug registers from being cleared # this will be fixed in later revisions of silicon -target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s # 4k working area at base of ram -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0 #flash configuration flash bank stellaris 0 0 0 0 0 diff --git a/src/target/target/lm3s811.cfg b/src/target/target/lm3s811.cfg index 90543334..e6a7d05f 100644 --- a/src/target/target/lm3s811.cfg +++ b/src/target/target/lm3s811.cfg @@ -1,5 +1,25 @@ # Script for luminary lm3s811 +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lm3s811 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a little endian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + # jtag speed jtag_khz 500 @@ -10,16 +30,16 @@ jtag_ntrst_delay 100 reset_config srst_only #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID # the luminary variant causes a software reset rather than asserting SRST # this stops the debug registers from being cleared # this will be fixed in later revisions of silicon -target create target0 cortex_m3 -endian little -chain-position 0 -variant lm3s +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s # 8k working area at base of ram -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0 #flash configuration flash bank stellaris 0 0 0 0 0 diff --git a/src/target/target/lpc2129.cfg b/src/target/target/lpc2129.cfg index d94f8228..a93d4992 100644 --- a/src/target/target/lpc2129.cfg +++ b/src/target/target/lpc2129.cfg @@ -1,12 +1,36 @@ #LPC-2129 CPU -#use combined on interfaces or targets that can’t set TRST/SRST separately + + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc2129 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + + +#use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4 +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 #flash bank <driver> <base> <size> <chip_width> <bus_width> flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum diff --git a/src/target/target/lpc2148.cfg b/src/target/target/lpc2148.cfg index 24ec05ed..7b701ab6 100644 --- a/src/target/target/lpc2148.cfg +++ b/src/target/target/lpc2148.cfg @@ -1,3 +1,23 @@ + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc2148 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + #delays on reset lines jtag_nsrst_delay 200 jtag_ntrst_delay 200 @@ -11,10 +31,12 @@ jtag_ntrst_delay 200 reset_config trst_and_srst srst_pulls_trst #jtag scan chain -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4 -[new_target_name] configure -event reset-init { +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 +$_TARGETNAME configure -event reset-init { # Force target into ARM state soft_reset_halt #do not remap 0x0000-0x0020 to anything but the flash @@ -22,7 +44,6 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 #flash bank lpc2000 <base> <size> 0 0 <target#> <variant> flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765 diff --git a/src/target/target/lpc2148_2mhz.cfg b/src/target/target/lpc2148_2mhz.cfg index 7e43f33d..0ed87ca4 100644 --- a/src/target/target/lpc2148_2mhz.cfg +++ b/src/target/target/lpc2148_2mhz.cfg @@ -1,3 +1,4 @@ # 2MHz jtag_khz 2000 script target/lpc2148.cfg + diff --git a/src/target/target/lpc2148_rclk.cfg b/src/target/target/lpc2148_rclk.cfg index 4a3fb3ef..dd7330f7 100644 --- a/src/target/target/lpc2148_rclk.cfg +++ b/src/target/target/lpc2148_rclk.cfg @@ -1,3 +1,4 @@ # RCLK jtag_khz 0 script target/lpc2148.cfg + diff --git a/src/target/target/lpc2294.cfg b/src/target/target/lpc2294.cfg index bd282eba..01ac5854 100644 --- a/src/target/target/lpc2294.cfg +++ b/src/target/target/lpc2294.cfg @@ -1,12 +1,31 @@ +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lpc2294 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4 -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 #flash configuration #flash bank lpc2000 <base> <size> 0 0 <target#> <variant> diff --git a/src/target/target/netx500.cfg b/src/target/target/netx500.cfg index e7b5e51a..c639017b 100644 --- a/src/target/target/netx500.cfg +++ b/src/target/target/netx500.cfg @@ -1,10 +1,34 @@ #Hilscher netX 500 CPU -#use combined on interfaces or targets that can’t set TRST/SRST separately + + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME netx500 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + + +#use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +# +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID jtag_nsrst_delay 100 jtag_ntrst_delay 100 -target create target0 arm926ejs -endian little -chain-position 0 -variant arm926ejs + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs diff --git a/src/target/target/nslu2.cfg b/src/target/target/nslu2.cfg index c545e01f..2ad71174 100644 --- a/src/target/target/nslu2.cfg +++ b/src/target/target/nslu2.cfg @@ -1,22 +1,8 @@ -# use combined on interfaces or targets that can't set TRST/SRST separately -reset_config srst_only - -# jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 7 0x1 0x7f 0x7e - -# target configuration -target create target0 xscale -endian big -chain-position 0 -variant ixp42x - - -# maps to PXA internal RAM. If you are using a PXA255 -# you must initialize SDRAM or leave this option off -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0 - -# flash bank <driver> <base> <size> <chip_width> <bus_width> -#flash bank cfi 0x50000000 0x1000000 2 4 0 - - +# This is for the LinkSys (CYSCO) LSLU2 board +# It is an Intel XSCALE IPX420 CPU. +source [find target/ipx42x.cfg] +# The _TARGETNAME is set by the above. +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0 diff --git a/src/target/target/omap5912.cfg b/src/target/target/omap5912.cfg index a18f8b71..5277593f 100644 --- a/src/target/target/omap5912.cfg +++ b/src/target/target/omap5912.cfg @@ -1,17 +1,38 @@ #TI OMAP5912 dual core processor - http://www.ti.com #on a OMAP5912 OSK board http://www.spectrumdigital.com. +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME omap5912 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 38 0x0 0x0 0x0 -jtag_device 4 0x1 0x0 0xe -jtag_device 8 0x0 0x0 0x0 +jtag newtap $_CHIPNAME unknown1 -irlen 38 -ircapture 0x0 -irmask 0x0 +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID +jtag newtap $_CHIPNAME unknown2 irlen 8 -ircapture 0x0 -irmask 0x0 + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs -target create target0 arm926ejs -endian little -chain-position 1 -variant arm926ejs -[new_target_name] configure -event reset-init { +$_TARGETNAME configure -event reset-init { # # halt target # @@ -36,7 +57,7 @@ target create target0 arm926ejs -endian little -chain-position 1 -variant arm926 } # omap5912 lcd frame buffer as working area -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0 +$_TARGENAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x3e800 -work-area-backup 0 #flash bank <driver> <base> <size> <chip_width> <bus_width> flash bank cfi 0x00000000 0x1000000 2 2 0 diff --git a/src/target/target/pic32mx.cfg b/src/target/target/pic32mx.cfg index 1d23ff2a..2ade5550 100644 --- a/src/target/target/pic32mx.cfg +++ b/src/target/target/pic32mx.cfg @@ -1,3 +1,23 @@ + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME pic32mx +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + jtag_nsrst_delay 100 jtag_ntrst_delay 100 @@ -6,13 +26,13 @@ reset_config srst_only #jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 5 0x1 0x1 0x1e +jtag newtap $_CPUNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME -target create target0 mips_m4k -endian little -chain-position 0 -[new_target_name] configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0 -#flash bank str7x <base> <size> 0 0 <target#> <variant> -#flash bank stm32x 0 0 0 0 0 # For more information about the configuration files, take a look at: # openocd.texi diff --git a/src/target/target/pxa255.cfg b/src/target/target/pxa255.cfg index de491f6d..c79ea4c9 100644 --- a/src/target/target/pxa255.cfg +++ b/src/target/target/pxa255.cfg @@ -1,9 +1,29 @@ -jtag_device 5 0x1 0x1f 0x1e +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME pxa255 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID + jtag_nsrst_delay 200 jtag_ntrst_delay 200 - -target create target0 xscale -endian little -chain-position 0 -variant pxa255 -[new_target_name] configure -event reset-init { +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa255 +$_TARGETNAME configure -event reset-init { xscale cp15 15 0x00002001 #Enable CP0 and CP13 access # # setup GPIO diff --git a/src/target/target/pxa255_sst.cfg b/src/target/target/pxa255_sst.cfg index 49ebd2b3..37ff1a8b 100644 --- a/src/target/target/pxa255_sst.cfg +++ b/src/target/target/pxa255_sst.cfg @@ -7,8 +7,9 @@ # RAM at 0x4000000 # Flash at 0x00000000 # -script target/pxa255.cfg +source [find target/pxa255.cfg] +# Target name is set by above +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0 # flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options] flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0 diff --git a/src/target/target/pxa270.cfg b/src/target/target/pxa270.cfg index dcf5fa2b..c745feb1 100644 --- a/src/target/target/pxa270.cfg +++ b/src/target/target/pxa270.cfg @@ -1,19 +1,43 @@ #Marvell/Intel PXA270 Script + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME pxa270 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + + # set jtag_nsrst_delay to the delay introduced by your reset circuit # the rest of the needed delays are built into the openocd program jtag_nsrst_delay 260 # set the jtag_ntrst_delay to the delay introduced by a reset circuit # the rest of the needed delays are built into the openocd program jtag_ntrst_delay 0 -#use combined on interfaces or targets that can’t set TRST/SRST separately +#use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst separate #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 7 0x1 0x7f 0x7e -target create target0 xscale -endian little -chain-position 0 -variant pxa27x + + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +jtag newtap $_TARGETNAME -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID + +target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x # maps to PXA internal RAM. If you are using a PXA255 # you must initialize SDRAM or leave this option off -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x5c000000 -work-area-size 0x10000 -work-area-backup 0 #flash bank <driver> <base> <size> <chip_width> <bus_width> # works for P30 flash diff --git a/src/target/target/s3c2440.cfg b/src/target/target/s3c2440.cfg index 6227107b..eba1a816 100644 --- a/src/target/target/s3c2440.cfg +++ b/src/target/target/s3c2440.cfg @@ -2,14 +2,36 @@ # Tested on a S3C2440 Evaluation board # Processor : ARM920Tid(wb) rev 0 (v4l) # Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) +# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places] +# [and I do not believe it to be accurate, hence the 0xffffffff below] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2440 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xFFFFFFFF +} #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID -target create target0 arm920t -endian little -chain-position 0 -variant arm920t +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1 #reset configuration reset_config trst_and_srst -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1 diff --git a/src/target/target/sam7se512.cfg b/src/target/target/sam7se512.cfg new file mode 100755 index 00000000..a3104058 --- /dev/null +++ b/src/target/target/sam7se512.cfg @@ -0,0 +1,38 @@ + +# ATMEL sam7se512 +# Example: the "Elektor Internet Radio" - EIR +# http://www.ethernut.de/en/hardware/eir/index.html + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sam7se512 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + +#use combined on interfaces or targets that can't set TRST/SRST separately +reset_config srst_only srst_pulls_trst + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +# The target +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 + +flash bank at91sam7 0 0 0 0 0 + diff --git a/src/target/target/sam7x256.cfg b/src/target/target/sam7x256.cfg index d7e11ff3..8e8cc97a 100644 --- a/src/target/target/sam7x256.cfg +++ b/src/target/target/sam7x256.cfg @@ -1,12 +1,30 @@ #use combined on interfaces or targets that can't set TRST/SRST separately reset_config srst_only srst_pulls_trst -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME sam7x256 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3f0f0f0f +} + +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi -[new_target_name] configure -event reset-init { +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi +$_TARGETNAME configure -event reset-init { # disable watchdog mww 0xfffffd44 0x00008000 # enable user reset @@ -25,7 +43,7 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm sleep 100 } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0 #flash bank <driver> <base> <size> <chip_width> <bus_width> flash bank at91sam7 0 0 0 0 0 diff --git a/src/target/target/samsung_s2c2410.cfg b/src/target/target/samsung_s2c2410.cfg new file mode 100755 index 00000000..3c0768bc --- /dev/null +++ b/src/target/target/samsung_s2c2410.cfg @@ -0,0 +1,35 @@ +# Found on the 'TinCanTools' Hammer board. + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2410 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # This config file was defaulting to big endian.. + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0xffffffff +} + +#use combined on interfaces or targets that cannot set TRST/SRST separately +reset_config trst_and_srst + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0 + +# speed up memory downloads +arm7_9 fast_memory_access enable +arm7_9 dcc_downloads enable diff --git a/src/target/target/samsung_s3c4510.cfg b/src/target/target/samsung_s3c4510.cfg new file mode 100755 index 00000000..65e7fd84 --- /dev/null +++ b/src/target/target/samsung_s3c4510.cfg @@ -0,0 +1,25 @@ + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c4510 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + + +# This appears to be a "Version 1" arm7tdmi. +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x1f0f0f0f +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + diff --git a/src/target/target/samsung_s3c6410.cfg b/src/target/target/samsung_s3c6410.cfg new file mode 100755 index 00000000..34078df9 --- /dev/null +++ b/src/target/target/samsung_s3c6410.cfg @@ -0,0 +1,49 @@ +# -*- tcl -*- +# Target configuration for the Samsung s3c6410 system on chip +# Tested on a SMDK6410 +# Processor : ARM1176 +# Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) +# [Duane Ellis 27/nov/2008: Above 0x0032409d appears to be copy/paste from other places] +# [and I do not believe it to be accurate, hence the 0xffffffff below] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c6410 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + # force an error till we get a good number + set _BSTAPID 0xffffffff +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + +#jtag scan chain + +# I think the "unknown" is the boundry scan tap +jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_BSTAPID +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -varient arm1176 + +jtag_nsrst_delay 500 +jtag_ntrst_delay 500 + +#reset configuration +reset_config trst_and_srst diff --git a/src/target/target/sharp_lh79532.cfg b/src/target/target/sharp_lh79532.cfg new file mode 100755 index 00000000..a239e3c5 --- /dev/null +++ b/src/target/target/sharp_lh79532.cfg @@ -0,0 +1,26 @@ +reset_config srst_only srst_pulls_trst + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lh79532 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # sharp changed the number! + set _CPUTAPID 0x00002061 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME + + diff --git a/src/target/target/smdk6410.cfg b/src/target/target/smdk6410.cfg index 0dd71742..6ce07cae 100644 --- a/src/target/target/smdk6410.cfg +++ b/src/target/target/smdk6410.cfg @@ -3,18 +3,6 @@ # Processor : ARM1176 # Info: JTAG device found: 0x0032409d (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0) -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe -jtag_device 5 0x1 0x1f 0xe - -#target create target0 arm11 -endian little -chain-position 0 -variant arm1176 -target arm11 little reset_halt 1 - -jtag_nsrst_delay 500 -jtag_ntrst_delay 500 - -#reset configuration -reset_config trst_and_srst +source [find target/samsung_s3c6410.cfg] flash bank cfi 0x00000000 0x00100000 2 2 0 jedec_probe
\ No newline at end of file diff --git a/src/target/target/stm32.cfg b/src/target/target/stm32.cfg index 1c80679e..c9581d49 100644 --- a/src/target/target/stm32.cfg +++ b/src/target/target/stm32.cfg @@ -1,5 +1,18 @@ # script for stm32 +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + + # jtag speed jtag_khz 500 @@ -10,15 +23,35 @@ jtag_ntrst_delay 100 reset_config trst_and_srst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe -jtag_device 5 0x1 0x1 0x1e - -target create target0 cortex_m3 -endian little -chain-position 0 +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 26.6.3 + set _CPUTAPID 0x3ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + # See STM Document RM0008 + # Section 26.6.2 + # Medium Density RevA + set _BSTAPID 0x06410041 + # Rev B and Rev Z + set _BSTAPID 0x16410041 + # High Density Devices, Rev A + set _BSTAPID 0x06414041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 -#flash bank str7x <base> <size> 0 0 <target#> <variant> flash bank stm32x 0 0 0 0 0 # For more information about the configuration files, take a look at: diff --git a/src/target/target/stm32stick.cfg b/src/target/target/stm32stick.cfg index 00964ab5..bb297dd7 100644 --- a/src/target/target/stm32stick.cfg +++ b/src/target/target/stm32stick.cfg @@ -1,5 +1,17 @@ # Hitex stm32 performance stick +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32_hitex +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + # set jtag speed jtag_khz 500 @@ -10,16 +22,28 @@ jtag_ntrst_delay 100 reset_config trst_and_srst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe -jtag_device 5 0x1 0x1 0x1e -jtag_device 4 0x1 0xf 0xe +# The CPU +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0008 + # Section 26.6.3 + set _CPUTAPID 0x3ba00477 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID + +# The boundery scan register, leave the "expected-id" undefined. +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e + +# What is this? It must be some extra chip on the stm32stick... +jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f -target create target0 cortex_m3 -endian little -chain-position 0 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 -#flash bank str7x <base> <size> 0 0 <target#> <variant> +# flash bank stm32x 0 0 0 0 0 # For more information about the configuration files, take a look at: diff --git a/src/target/target/str710.cfg b/src/target/target/str710.cfg index b2e03f3d..de3b0b9e 100644 --- a/src/target/target/str710.cfg +++ b/src/target/target/str710.cfg @@ -1,23 +1,42 @@ #start slow, speed up after reset jtag_khz 10 +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str710 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0xffffffff +} + #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi -[new_target_name] configure -event reset-start { jtag_khz 10 } -[new_target_name] configure -event reset-init { jtag_khz 6000 } -[new_target_name] configure -event gdb-flash-erase-start { +tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi +$_TARGETNAME configure -event reset-start { jtag_khz 10 } +$_TARGETNAME configure -event reset-init { jtag_khz 6000 } +$_TARGETNAME configure -event gdb-flash-erase-start { flash protect 0 0 7 off flash protect 1 0 1 off } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-area-backup 0 #flash bank str7x <base> <size> 0 0 <target#> <variant> flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x diff --git a/src/target/target/str730.cfg b/src/target/target/str730.cfg index 8c0f59c4..c0dfcdd1 100644 --- a/src/target/target/str730.cfg +++ b/src/target/target/str730.cfg @@ -1,29 +1,46 @@ #STR730 CPU - jtag_khz 3000 +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str730 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0xffffffff +} + -#use combined on interfaces or targets that can’t set TRST/SRST separately +#use combined on interfaces or targets that can't set TRST/SRST separately #reset_config trst_and_srst srst_pulls_trst reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID #jtag nTRST and nSRST delay jtag_nsrst_delay 500 jtag_ntrst_delay 500 -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi -[new_target_name] configure -event reset-start { jtag_khz 10 } -[new_target_name] configure -event reset-init { jtag_khz 3000 } -[new_target_name] configure -event gdb-flash-erase-start { +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi +$_TARGETNAME configure -event reset-start { jtag_khz 10 } +$_TARGETNAME configure -event reset-init { jtag_khz 3000 } +$_TARGETNAME configure -event gdb-flash-erase-start { flash protect 0 0 7 off } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 #flash bank <driver> <base> <size> <chip_width> <bus_width> flash bank str7x 0x20000000 0x00040000 0 0 0 STR3x diff --git a/src/target/target/str750.cfg b/src/target/target/str750.cfg index 6d0c47d3..806bbfa1 100644 --- a/src/target/target/str750.cfg +++ b/src/target/target/str750.cfg @@ -1,31 +1,50 @@ #STR750 CPU +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str750 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0xffffffff +} + # jtag speed jtag_khz 10 -#use combined on interfaces or targets that can’t set TRST/SRST separately +#use combined on interfaces or targets that can't set TRST/SRST separately #reset_config trst_and_srst srst_pulls_trst reset_config trst_and_srst srst_pulls_trst #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe + +tag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID #jtag nTRST and nSRST delay jtag_nsrst_delay 500 jtag_ntrst_delay 500 -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi -[new_target_name] configure -event reset-start { jtag_khz 10 } -[new_target_name] configure -event reset-init { jtag_khz 3000 } -[new_target_name] configure -event gdb-flash-erase-start { +$_TARGETNAME configure -event reset-start { jtag_khz 10 } +$_TARGETNAME configure -event reset-init { jtag_khz 3000 } +$_TARGETNAME configure -event gdb-flash-erase-start { flash protect 0 0 7 off flash protect 1 0 1 off } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0 #flash bank <driver> <base> <size> <chip_width> <bus_width> flash bank str7x 0x20000000 0x00040000 0 0 0 STR75x diff --git a/src/target/target/str910-eval.cfg b/src/target/target/str910-eval.cfg index 276bb48a..44edeaa4 100644 --- a/src/target/target/str910-eval.cfg +++ b/src/target/target/str910-eval.cfg @@ -3,13 +3,44 @@ # Need reset scripts reset_config trst_and_srst -jtag_device 8 0x1 0x1 0xfe -jtag_device 4 0x1 0xf 0xe -jtag_device 5 0x1 0x1 0x1e +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str912 +} -target arm966e little reset_halt 1 arm966e +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} -working_area 0 0x50000000 16384 nobackup +if { [info exists FLASHTAPID ] } { + set _FLASHTAPID $FLASHTAPID +} else { + # Fixme with a correct number! + set _FLASHTAPID 0xFFFFFFFF +} +jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0xfe -expected-id $_FLASHTAPID + + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966041 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_CPUTAPID + +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + set _BSTAPID 0xFFFFFFFF +} +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e -expected-id $_BSTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e +$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1 flash bank str9xpec 0x00000000 0x00080000 0 0 0 diff --git a/src/target/target/str912.cfg b/src/target/target/str912.cfg index 6f605b06..3b7d7ff1 100644 --- a/src/target/target/str912.cfg +++ b/src/target/target/str912.cfg @@ -1,29 +1,58 @@ # script for str9 -# jtag speed. We need to stick to 16kHz until we've finished reset. +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME str912 +} -jtag_rclk 16 +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# jtag speed. We need to stick to 16kHz until we've finished reset. +jtag_rclk 16 + jtag_nsrst_delay 100 jtag_ntrst_delay 100 #use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst -#jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 8 0x1 0x1 0xfe -jtag_device 4 0x1 0xf 0xe -jtag_device 5 0x1 0x1 0x1e +if { [info exists FLASHTAPID ] } { + set _FLASHTAPID $FLASHTAPID +} else { + set _FLASHTAPID 0x25966041 +} +jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0xfe -expected-id $_FLASHTAPID + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966041 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_CPUTAPID + + +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + set _BSTAPID 0x1457f041 +} +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1e -expected-id $_BSTAPID -target create target0 arm966e -endian little -chain-position 1 -variant arm966e +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e -[new_target_name] configure -event reset-start { jtag_rclk 16 } +$_TARGETNAME configure -event reset-start { jtag_rclk 16 } -[new_target_name] configure -event reset-init { +$_TARGETNAME configure -event reset-init { # We can increase speed now that we know the target is halted. - jtag_rclk 3000 + #jtag_rclk 3000 # -- Enable 96K RAM # PFQBC enabled / DTCM & AHB wait-states disabled @@ -33,7 +62,7 @@ target create target0 arm966e -endian little -chain-position 1 -variant arm966e flash protect 0 0 7 off } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0 #flash bank str9x <base> <size> 0 0 <target#> <variant> flash bank str9x 0x00000000 0x00080000 0 0 0 diff --git a/src/target/target/str9comstick.cfg b/src/target/target/str9comstick.cfg index b9b5fc75..0696c121 100644 --- a/src/target/target/str9comstick.cfg +++ b/src/target/target/str9comstick.cfg @@ -5,15 +5,38 @@ jtag_khz 3000 jtag_nsrst_delay 100 jtag_ntrst_delay 100 -#use combined on interfaces or targets that can’t set TRST/SRST separately +#use combined on interfaces or targets that can't set TRST/SRST separately reset_config trst_and_srst #jtag scan chain #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 8 0x1 0x1 0xfe -jtag_device 4 0x1 0xf 0xe -jtag_device 5 0x1 0x1 0x1e -target create target0 arm966e -endian little -chain-position 1 -variant arm966e -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0 + + +if { [info exists FLASHTAPID ] } { + set _FLASHTAPID $FLASHTAPID +} else { + set _FLASHTAPID 0xFFFFFFFF +} +jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x25966041 +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xf -irmask 0xe -expected-id $_CPUTAPID + + +if { [info exists BSTAPID ] } { + set _BSTAPID $BSTAPID +} else { + set _BSTAPID 0xFFFFFFFF +} +jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e + +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0 #flash bank <driver> <base> <size> <chip_width> <bus_width> flash bank str9x 0x00000000 0x00080000 0 0 0 diff --git a/src/target/target/test_reset_syntax_error.cfg b/src/target/target/test_reset_syntax_error.cfg index b720ca9d..e573c1c0 100644 --- a/src/target/target/test_reset_syntax_error.cfg +++ b/src/target/target/test_reset_syntax_error.cfg @@ -4,12 +4,14 @@ # at91eb40a target #jtag scan chain -jtag_device 4 0x1 0xf 0xe +set _CHIPNAME syntaxtest +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf #target configuration -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 -[new_target_name] configure -event reset-init { +$_TARGETNAME configure -event reset-init { syntax error } diff --git a/src/target/target/wi-9c.cfg b/src/target/target/wi-9c.cfg index a966f54c..3606d0d5 100644 --- a/src/target/target/wi-9c.cfg +++ b/src/target/target/wi-9c.cfg @@ -1,15 +1,37 @@ +# FIXME: THIS IS A *BOARD* not a CHIP configuration. ###################################### # Target: DIGI ConnectCore Wi-9C ###################################### reset_config trst_and_srst +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME ns9360 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # This config file was defaulting to big endian.. + set _ENDIAN big +} + + # What's a good fallback frequency for this board if RCLK is # not available?? jtag_rclk 1000 -#jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction> -jtag_device 4 0x1 0xf 0xe + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0xFFFFFFFF +} + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +jtag newtap_device $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID jtag_nsrst_delay 200 jtag_ntrst_delay 0 @@ -19,8 +41,8 @@ jtag_ntrst_delay 0 # Target configuration ###################### -target create target0 arm926ejs -endian big -chain-position 0 -variant arm926ejs -[new_target_name] configure -event reset-init { +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs +$_TARGETNAME configure -event reset-init { mww 0x90600104 0x33313333 mww 0xA0700000 0x00000001 # Enable the memory controller. mww 0xA0700024 0x00000006 # Set the refresh counter 6 @@ -92,7 +114,7 @@ target create target0 arm926ejs -endian big -chain-position 0 -variant arm926ejs reg cpsr 0xd3 } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1 ##################### # Flash configuration diff --git a/src/target/target/xba_revA3.cfg b/src/target/target/xba_revA3.cfg index 30d119a8..007cb9e1 100644 --- a/src/target/target/xba_revA3.cfg +++ b/src/target/target/xba_revA3.cfg @@ -1,16 +1,36 @@ #Written by: Michael Schwingen <rincewind@discworld.dascon.de> +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME xba_reva3 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # default to big endian + set _ENDIAN big +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0xffffffff +} + reset_config trst_and_srst separate jtag_nsrst_delay 100 jtag_ntrst_delay 100 #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR capture Mask, IDCODE) -jtag_device 7 0x1 0x7f 0x7e +jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -target create target0 xscale -endian big -chain-position 0 -variant ixp42x -[new_target_name] configure -event reset-init { +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x +$_TARGETNAME configure -event reset-init { ############################################################################# # setup expansion bus CS, disable external wdt ############################################################################# @@ -55,7 +75,7 @@ target create target0 xscale -endian big -chain-position 0 -variant ixp42x flash probe 0 } -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20010000 -work-area-size 0x8060 -work-area-backup 0 flash bank cfi 0x50000000 0x400000 2 2 0 diff --git a/src/target/target/zy1000.cfg b/src/target/target/zy1000.cfg index 2fb2db32..56bf0c46 100644 --- a/src/target/target/zy1000.cfg +++ b/src/target/target/zy1000.cfg @@ -8,19 +8,39 @@ #SRST reset, which means that the CPU will run a number #of cycles before it can be halted(as much as milliseconds). reset_config srst_only srst_pulls_trst + + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME zy1000 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + #jtag scan chain -#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE) -jtag_device 4 0x1 0xf 0xe +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # sharp changed the number! + set _CPUTAPID 0x3f0f0f0f +} +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi-s_r4 +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4 # at CPU CLK <32kHz this must be disabled arm7_9 fast_memory_access enable arm7_9 dcc_downloads enable flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf -[new_target_name] configure -event reset-init { +$_TARGETNAME configure -event reset-init { # Set up chip selects & timings mww 0xFFE00000 0x0100273D mww 0xFFE00004 0x08002125 @@ -44,7 +64,7 @@ flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf # required for usable performance. Used for lots of # other things than flash programming. -[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0 +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0 jtag_khz 16000 |