diff options
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/arm926ejs.c | 8 | ||||
| -rw-r--r-- | src/target/cortex_a8.c | 112 |
2 files changed, 97 insertions, 23 deletions
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c index 8cb5dbe0..3c808021 100644 --- a/src/target/arm926ejs.c +++ b/src/target/arm926ejs.c @@ -277,7 +277,7 @@ int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t return ERROR_OK; } -int arm926ejs_examine_debug_reason(target_t *target) +static int arm926ejs_examine_debug_reason(target_t *target) { armv4_5_common_t *armv4_5 = target->arch_info; arm7_9_common_t *arm7_9 = armv4_5->arch_info; @@ -294,7 +294,11 @@ int arm926ejs_examine_debug_reason(target_t *target) switch (debug_reason) { - /* case 0: no debug entry */ + case 0: + LOG_DEBUG("no *NEW* debug entry (?missed one?)"); + /* ... since last restart or debug reset ... */ + target->debug_reason = DBG_REASON_DBGRQ; + break; case 1: LOG_DEBUG("breakpoint from EICE unit 0"); target->debug_reason = DBG_REASON_BREAKPOINT; diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c index f6f13cfc..846d90c3 100644 --- a/src/target/cortex_a8.c +++ b/src/target/cortex_a8.c @@ -67,6 +67,8 @@ int cortex_a8_dap_read_coreregister_u32(target_t *target, uint32_t *value, int regnum); int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum); +int cortex_a8_assert_reset(target_t *target); +int cortex_a8_deassert_reset(target_t *target); target_type_t cortexa8_target = { @@ -81,8 +83,8 @@ target_type_t cortexa8_target = .resume = cortex_a8_resume, .step = cortex_a8_step, - .assert_reset = NULL, - .deassert_reset = NULL, + .assert_reset = cortex_a8_assert_reset, + .deassert_reset = cortex_a8_deassert_reset, .soft_reset_halt = NULL, .get_gdb_reg_list = armv4_5_get_gdb_reg_list, @@ -138,8 +140,13 @@ int cortex_a8_init_debug_access(target_t *target) /* Clear Sticky Power Down status Bit in PRSR to enable access to the registers in the Core Power Domain */ retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy); - /* Enabling of instruction execution in debug mode is done in debug_entry code */ - + /* Enabling of instruction execution in debug mode is done in debug_entry code */ + + /* Resync breakpoint registers */ + + /* Since this is likley called from init or reset, update targtet state information*/ + cortex_a8_poll(target); + return retval; } @@ -158,8 +165,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) + { + LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode); return retval; } + } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode); @@ -169,8 +179,11 @@ int cortex_a8_exec_opcode(target_t *target, uint32_t opcode) retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr); if (retval != ERROR_OK) + { + LOG_ERROR("Could not read DSCR register"); return retval; } + } while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */ return retval; @@ -223,11 +236,25 @@ int cortex_a8_write_cp(target_t *target, uint32_t value, uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2) { int retval; + uint32_t dscr; + /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info; swjdp_common_t *swjdp = &armv7a->swjdp_info; + LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value); + + /* Check that DCCRX is not full */ + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (dscr & (1 << DSCR_DTR_RX_FULL)) + { + LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); + /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ + cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); + } + retval = mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_DTRRX, value); /* Move DTRRX to r0 */ @@ -298,12 +325,25 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r { int retval = ERROR_OK; uint8_t Rd = regnum&0xFF; + uint32_t dscr; /* get pointers to arch-specific information */ armv4_5_common_t *armv4_5 = target->arch_info; armv7a_common_t *armv7a = armv4_5->arch_info; swjdp_common_t *swjdp = &armv7a->swjdp_info; + + LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value); + /* Check that DCCRX is not full */ + retval = mem_ap_read_atomic_u32(swjdp, + armv7a->debug_base + CPUDBG_DSCR, &dscr); + if (dscr & (1 << DSCR_DTR_RX_FULL)) + { + LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr); + /* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode 0xEE000E15 */ + cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0)); + } + if (Rd > 16) return retval; @@ -1188,6 +1228,33 @@ int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoin * Cortex-A8 Reset fuctions */ +int cortex_a8_assert_reset(target_t *target) +{ + + LOG_DEBUG(" "); + + /* registers are now invalid */ + armv4_5_invalidate_core_regs(target); + + target->state = TARGET_RESET; + + return ERROR_OK; +} + +int cortex_a8_deassert_reset(target_t *target) +{ + + LOG_DEBUG(" "); + + if (target->reset_halt) + { + int retval; + if ((retval = target_halt(target)) != ERROR_OK) + return retval; + } + + return ERROR_OK; +} /* * Cortex-A8 Memory access @@ -1265,22 +1332,25 @@ int cortex_a8_write_memory(struct target_s *target, uint32_t address, exit(-1); } - /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ - /* invalidate I-Cache */ - if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + if (target->state == TARGET_HALTED) { - /* Invalidate ICache single entry with MVA, repeat this for all cache - lines in the address range, Cortex-A8 has fixed 64 byte line length */ - /* Invalidate Cache single entry with MVA to PoU */ - for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) - armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */ - } - /* invalidate D-Cache */ - if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) - { - /* Invalidate Cache single entry with MVA to PoC */ - for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) - armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */ + /* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */ + /* invalidate I-Cache */ + if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled) + { + /* Invalidate ICache single entry with MVA, repeat this for all cache + lines in the address range, Cortex-A8 has fixed 64 byte line length */ + /* Invalidate Cache single entry with MVA to PoU */ + for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) + armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */ + } + /* invalidate D-Cache */ + if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) + { + /* Invalidate Cache single entry with MVA to PoC */ + for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64) + armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */ + } } return retval; @@ -1374,7 +1444,7 @@ int cortex_a8_examine(struct target_s *target) uint32_t didr, ctypr, ttypr, cpuid; LOG_DEBUG("TODO"); - + /* Here we shall insert a proper ROM Table scan */ armv7a->debug_base = OMAP3530_DEBUG_BASE; @@ -1451,7 +1521,7 @@ int cortex_a8_examine(struct target_s *target) /* Configure core debug access */ cortex_a8_init_debug_access(target); - + target->type->examined = 1; return retval; |