diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/helper/startup.tcl | 30 | ||||
| -rw-r--r-- | src/jtag/core.c | 6 |
2 files changed, 26 insertions, 10 deletions
diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl index 229aa066..b12d02bb 100644 --- a/src/helper/startup.tcl +++ b/src/helper/startup.tcl @@ -134,6 +134,23 @@ proc ocd_gdb_restart {target_id} { reset halt } + +# This reset logic may be overridden by board/target/... scripts as needed +# to provide a reset that, if possible, is close to a power-up reset. +# +# Exit requirements include: (a) JTAG must be working, (b) the scan +# chain was validated with "jtag arp_init" (or equivalent), (c) nothing +# stays in reset. No TAP-specific scans were performed. It's OK if +# some targets haven't been reset yet; they may need TAP-specific scans. +# +# The "mode" values include: halt, init, run (from "reset" command); +# startup (at OpenOCD server startup, when JTAG may not yet work); and +# potentially more (for reset types like cold, warm, etc) +proc init_reset { mode } { + jtag arp_init-reset +} + + global in_process_reset set in_process_reset 0 @@ -189,10 +206,7 @@ proc ocd_process_reset_inner { MODE } { # Use TRST or TMS/TCK operations to reset all the tap controllers. # TAP reset events get reported; they might enable some taps. - # - # REVISIT arp_init-reset pulses SRST (if it can) with TRST active; - # but SRST events aren't reported (unlike "jtag arp_reset", below) - jtag arp_init-reset + init_reset $MODE # Examine all targets on enabled taps. foreach t $targets { @@ -361,11 +375,11 @@ proc capture_catch {a} { } -# Executed during "init". Can be implemented by target script -# tar +# Executed during "init". Can be overridden +# by board/target/... scripts proc jtag_init {} { if {[catch {jtag arp_init} err]!=0} { # try resetting additionally - jtag arp_init-reset + init_reset startup } -}
\ No newline at end of file +} diff --git a/src/jtag/core.c b/src/jtag/core.c index bdfd6e5b..1c9d13c9 100644 --- a/src/jtag/core.c +++ b/src/jtag/core.c @@ -973,8 +973,9 @@ static bool jtag_examine_chain_end(uint8_t *idcodes, unsigned count, unsigned ma for (; count < max - 31; count += 32) { uint32_t idcode = buf_get_u32(idcodes, count, 32); - // do not trigger the warning if the data looks good - if (!triggered && jtag_idcode_is_final(idcode)) + + /* do not trigger the warning if the data looks good */ + if (jtag_idcode_is_final(idcode)) continue; LOG_WARNING("Unexpected idcode after end of chain: %d 0x%08x", count, (unsigned int)idcode); @@ -1027,6 +1028,7 @@ static int jtag_examine_chain(void) /* DR scan to collect BYPASS or IDCODE register contents. * Then make sure the scan data has both ones and zeroes. */ + LOG_DEBUG("DR scan interrogation for IDCODE/BYPASS"); retval = jtag_examine_chain_execute(idcode_buffer, JTAG_MAX_CHAIN_SIZE); if (retval != ERROR_OK) return retval; |