diff options
Diffstat (limited to 'tcl/board/at91sam9g20-ek.cfg')
| -rw-r--r-- | tcl/board/at91sam9g20-ek.cfg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tcl/board/at91sam9g20-ek.cfg b/tcl/board/at91sam9g20-ek.cfg index c9deb144..00ab7faf 100644 --- a/tcl/board/at91sam9g20-ek.cfg +++ b/tcl/board/at91sam9g20-ek.cfg @@ -62,7 +62,7 @@ proc read_register {register} { } proc at91sam9g20_init { } { - + # At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz). To shift over to a normal clock requires # a number of steps that must be carefully performed. The process outline below follows the # recommended procedure outlined in the AT91SAM9G20 technical manual. @@ -94,7 +94,7 @@ proc at91sam9g20_init { } { mww 0xfffffc30 0x00000101 while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 } - + # Now change PMC_MCKR register to select PLLA. # Wait for MCKRDY signal from PMC_SR to assert. |